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WorksheetsEC8552-Computer Architecture
Total questions: 53
Worksheet time: 53mins
Which of the following is true about Computer Architecture?
It acts as the interface between hardware and software.
Computer Architecture tells us how exactly all the units in the system are arranged and interconnected.
Computer Architecture is concerned with the structure and behaviour of a computer system as seen by the user.
It involves Physical Component
The register which holds the address of the location to or from which data are to be transferred is called
Index Register
Instruction Register
Memory Address Register
Memory Data Register
The device which is used to connect a peripheral to bus is called . Control register B. Interface C. Communication protocol D. None of these
Control Register
Interface
Communication Protocol
None of these
The register used as a working area in CPU is
Program Counter
Instruction Register
Instruction Decoder
Accumualtor
Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed ?
Accumulator
Index Register
Instruction Decoder
Program Counter
The function of program counter (PC) holds
Temporary
Address for Memory
memory Operand
Address of Instruction
Which of the following is not a form of memory ?
Instruction Cache
Instruction Register
Instruction Opcode
Both (A) and (B)
A dynamic RAM consists of
6 Transistors
2 Transistors and 2 Capacitors
1 Transistor and 1 capacitor
None of These
A new switching device was used in second generation
Vacuum tubes
Transistors
Diodes
It is known that we get more throughput by performing operations in parallel
Pipelining via Parallelism
Performance via Parallelism
Performance via Pipelining
Processor support parallelism concept
Uni processor
Multi Processor
intel Processor
MOV R2, R1
Register Addressing mode
Direct Addressing mode
Indirect Addressing mode
Locations for source and destination operands
Main or virtual memory
Secondary memory
Primary memory
Computer use addressing mode techniques for
giving performance versatility to the user by providing facilities as pointers to memory counters for loop control
to reduce no. of bits in the field of instruction
specifying rules for modifying or interpreting address field of the instruction
all the above
In computer subtraction is generally carried out by
10's complement
1's complement
2's complement
Part-B
Write a program to evaluate the arithmetic statement : Y=(A+B)*(C+D) using three address
ADD R1, A,B
ADD R2, C,D
MUL Y, R1,R2
MUL R1, A,B
ADD R2, C,D
ADD Y, R1,R2
ADD R1, A,B
MUL R2, C,D
MUL Y, R1,R2
Indexed addressing mode
MOV BX, [SI+16]
MOV BX, [SI+8],
MOV BX, [I+16],
Two complement representation of (-3)
1101
1010
0011
In signed magnitude binary division if the dividend is (111000)2 and divisor is (10011)2 then the result is
(00100)2
(10100)2
(11001)2
(01100)2
The transfer between CPU and Cache is ______________
Word transfer
Block transfer
Set transfer
Associative transfer
What is the high speed memory between the main memory and the CPU called?
Register Memory
Storage Memory
Cache Memory
Virtual Memory
Which chips are used for the implementation of Cache Memory?
DRAM
SRAM
Onboard
onchip
The formula to calculate the Miss Rate is ___________
Number of Hits / Total Attempt
Number of misses / Total Attempt
Total Attempt / Number of Misses
Total Attempt / Number of Hits
___________________________ means current data or instruction that is being fetched may be needed soon.
Temporal Locality
Spatial Locality
Memory Reference
Space Reference
Which device is used to back up the data?
Floppy Disk
Tapes
Network Drive
Cloud Storage
The fetch and execution cycles are interleaved with the help of ________
Modification in processor architecture
Clock
Special unit
Control unit
To increase the speed of memory access in pipelining, we make use of _______
Special memory locations
Special purpose registers
Cache
Buffers
The situation wherein the data of operands are not available is called ______
Data hazard
Stock
Deadlock
Structural hazard
What does the hardwired control generator consist of?
Decoder/encoder
Condition codes
Control step counter
All of the mentioned
The _________ controls the I/O devices and transfer of data to and from the primary storage.
LU
AU
ALU
CU
____________ enables the processor to access data quickly whenever they are needed.
CU
Cache
Memory
Register
The set of wires, which carry information in a controlled manner, is called
System bus
Public bus
Private bus
None of these
The ALU works on the instructions and data held in the _______________
Notebook
Registers
Copy Pad
I/O devices
A register that keeps track of the next instruction to be executed is called a _____________
Program Counter
Instruction Register
Accumulator
Data Register
_______________ is a large multilayered printed circuit board inside a computer that contains CPU,BIOS,ROM chip and the CMOS setup information.
Motherboard
RAM
ROM
Cache
The ___________ informs the CPU about the location of the data residing in the memory.
Data bus
Address bus
Cache
Control line
Which one of the following is the smallest memory ?
Main Memory
Cache
Registers
External Memory
Can I/O Modules directly access the memory without involving the processor?
Yes
No
Multiple interrupts are possible during the program execution.
True
False
What is fetch function in machine cycle ?
Fetch instruction from control unit to memory
Fetch instruction from memory to control unit
Fetch instruction from control unit to arithmetic logic unit
What are 3 types of registers in CPU
Program Counter Register, Instruction Register, Status Register
Program State Register, Instruction Register, Status Register
Program State Register, Instruction Register, Flag Register
It acts as a temporary storage area that the computer's processor can retrieve data from easily. This statement refers to
Control Unit
Cache
Cookies
Which statement is FALSE about static random access memory (SRAM)
Faster than DRAM and more expensive than DR AM
Frequently small amount used in cache memory for high-speed access used
Non Volatile
How many locations in a memory if size of the address is 8 bits
16 locations
64 locations
256 locations
VLSI stands for ___________
Very Large Scale Integration
Very Large Stand-alone Integration
Volatile Layer System Interface
None of the mentioned
How is memory accessed in RISC architecture?
load and store instruction
opcode instruction
memory instruction
bus instruction
Computer memory which allows simultaneous read and write operation is
ROM
RAM
EPROM
EEPROM
The CISC stands for ___________
Computer Instruction Set Compliment
Complete Instruction Set Compliment
Computer Indexed Set Components
Complex Instruction set computer
Pipe-lining is a unique feature of _______
CISC
RISC
ISA
ANNA
ROM has the capability to perform _____________
Write operation only
Read operation only
Both write and read operation
Erase operation
