WorksheetsMODEL III _ EC8552 _ CAO _ PART B_25.11.2020
Total questions: 15
Worksheet time: 15mins
Name
Class
Date
1.
For a certain program with 1,00,00,000 instructions, find the execution time given the average CPI is 2.5 cycles/instruction and clock rate as 200MHz.
a)
0.125 s
b)
0.135 s
c)
0.145 s
d)
0.155 s
2.
Suppose we developed a new, simpler processor that has 85% of the capacitive load of the more complex older processor. Further, assume that it has adjustable voltage so that it can reduce voltage 1 5% compared to processor B, which results in 15% shrink in frequency. What is the impact on dynamic power? Given: 85% of capacitive load of old CPU, 15% voltage reduction, 15% frequency reduction
a)
0.57
b)
0.67
c)
0.62
d)
0.52
3.
A program runs in 10 seconds on computer A, which has a 2 GHz clock. We are trying to help a computer designer build a computer, B, which with run this program in 6 seconds. The designer has determined that a substantial increase in the clock rate is possible, but this increase will affect the rest of the CPU design, causing computer B to require 1.2 time as many clock cycles as computer A for this program. What clack rate should we tell the designer to target?
a)
2Ghz
b)
3Ghz
c)
4Ghz
d)
5Ghz
4.
If the multiplier QR is 101101001, how many add operations are performed in booth multiplication process to reach final product?
a)
(A) 4
b)
(B) 5
c)
(C) 3
d)
(D) 2
5.
Add the two magnitudes when the signs of A & B are ________ in addition algorithm and _________ in subtraction algorithm.
a)
(A) identical, identical
b)
(B) different, identical
c)
(C) different, different
d)
(D) identical, different
6.
Express the decimal format of the signed binary number (101010)2 .
a)
a) 10
b)
b) 12
c)
c) -12
d)
d) -10
7.
<br />If the stages are perfectly balanced, then the time per instruction on the pipelined processor, is equal to
a)
Time per instruction on unpipelined machine/ no of piped stages
b)
Time per instruction on unpipelined machine* no of piped stages
c)
Time per instruction on unpipelined machine + no of piped stages
d)
Time per instruction on unpipelined machine - no of piped stages
8.
Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operationsand branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is
a)
4.4 ns
b)
4.2 ns
c)
3.4 ns
d)
3.2 ns
9.
Register $2 written by subtraction can be written in the instruction
a)
sub $4, $1,$3
b)
sub $2, $1,$3
c)
add $2, $1,$3
d)
mul $2, $1,$3
10.
When process requests for a DMA transfer ,
a)
Then the process is temporarily suspended
b)
The process continues execution
c)
Another process gets executed
d)
Both a and c
11.
Consider a two-level cache hierarchy L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experience on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is ______________.
a)
0.05
b)
0.06
c)
0.07
d)
0.08
12.
<br />A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.
a)
12
b)
14
c)
16
d)
18
13.
Consider there are four levels of 2 X 2 switch as a building block in multistage switching network. We can connect how many memories as binary strings?
a)
4
b)
8
c)
16
d)
32
14.
In a network with 25 computers, which topology would require the most extensive cabling?
a)
bus
b)
mesh
c)
star
d)
tree
15.
In order to prevent a fast sender from swamping a slow receiver with data, feedback is often used. This process is known as-
a)
flow control
b)
multiplexing
c)
congestion
d)
none of the mentioned
100 %
