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WorksheetsComputer architecture
Total questions: 51
Worksheet time: 26mins
Example of user visible register
MDR
General Purpose Reg
IR
PC
Segment Register is a _____register
General Purpose
Address Reg
Data Reg
Example of control and staus register
General Purpose Reg
Data Reg
Address Reg
PC
Program Counter (PC) stores
Address
Data
Instruction
Instruction Reg (IR) stores
Address
Instruction
Data
Register and ALU communicates through
Address Bus
Data Bus
Internal CPU bus
The data read from memory is stored in to
MAR
IR
MDR
The data read from memory is stored in to
MAR
IR
MDR
Address of memory location where we need to read or write is stored in
MAR
MDR
PC
After fetch cycle the CPU will execute which cycle?
Interrupt Cycle
Execute Cycle
Execute or Indirect Cycle
After indirect cycle the cpu will perform
Fetch cycle
Interupt Cycle
Execute Cycle
The direction of data flow in fetch cycle is
towards CPU
Towards Memory
Both Direction
The direction of data flow in data bus at interrupt cycle
towards cpu
towards memry
both direction
In interrupt cycle MAR get address from
PC
IR
Control Unit
In fetch cycle MAR gets address from
PC
Control Umit
MDR
In indirect cycle MAR gets address from
PC
Control Unit
MDR
The _________ controls the I/O devices and transfer of data to and from the primary storage.
LU
AU
ALU
CU
____________ enables the processor to access data quickly whenever they are needed.
CU
Cache
Memory
Register
The set of wires, which carry information in a controlled manner, is called
System bus
Public bus
Private bus
None of these
The ALU works on the instructions and data held in the _______________
Notebook
Registers
Copy Pad
I/O devices
The ALU works on the instructions and data held in the _______________
Notebook
Registers
Copy Pad
I/O devices
The fastest memory in the computer system is _____________
ROM
RAM
Cache
None of these
The fastest memory in the computer system is _____________
ROM
RAM
Cache
None of these
A register that keeps track of the next instruction to be executed is called a _____________
Program Counter
Instruction Register
Accumulator
Data Register
A processor only operates on binary data, that is, data composed of 1s and 0s.
True
False
The address bus informs the CPU about the location of of the data residing in the memory.
The address bus informs the CPU about the location of of the data residing in the memory.
The L2 cache is usually 64KB - 2MB in size.
_______________ is a large multilayered printed circuit board inside a computer that contains CPU,BIOS,ROM chip and the CMOS setup information.
Motherboard
RAM
ROM
Cache
The ___________ informs the CPU about the location of the data residing in the memory.
Data bus
Address bus
Cache
Control line
This picture represents
Harvard Architecture
Von Nuemann Architecture
IBM Architecture
The north bridge of a motherboard will connected to CPU in
low speed transmission
high speed transmission
both low & high speed transmission
What is a function of arithmetic & logic unit(ALU)
Performs calculations and comparisons (data changed)
Performs a data exchanged and calculations
Perform data manipulation and coordination
What is fetch function in machine cycle ?
Fetch instruction from control unit to memory
Fetch instruction from memory to control unit
Fetch instruction from control unit to arithmetic logic unit
What are 3 types of registers in CPU
Program Counter Register, Instruction Register, Status Register
Program State Register, Instruction Register, Status Register
Program State Register, Instruction Register, Flag Register
It acts as a temporary storage area that the computer's processor can retrieve data from easily. This statement refers to
Control Unit
Cache
Cookies
Which statement is FALSE about static random access memory (SRAM)
Faster than DRAM and more expensive than DR AM
Frequently small amount used in cache memory for high-speed access used
Non Volatile
Which statement is FALSE about static random access memory (SRAM)
Faster than DRAM and more expensive than DR AM
Frequently small amount used in cache memory for high-speed access used
Non Volatile
Which factor can determine a memory capacity?
No of bits in Memory Address Register(MAR)
No of bits in Memory Data Register(MDR)
No of bits in Random Access Memory(RAM)
Which statement is TRUE about SRAM(static RAM) and DRAM(dynamic RAM)?
DRAM is faster than SRAM
DRAM is cheaper than SRAM
DRAM and SRAM is nonvolatile memory
How many locations in a memory if size of the address is 8 bits
16 locations
64 locations
256 locations
The register which holds the address of the location to or from which data are to be transferred is called
Index Register
Instruction Register
Memory Address Register
Memory Data Register
The register used as a working area in CPU is
Program Counter
Instruction Register
Instruction Decoder
Accumualtor
The device which is used to connect a peripheral to bus is called . Control register B. Interface C. Communication protocol D. None of these
Control Register
Interface
Communication Protocol
None of these
Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed ?
Accumulator
Index Register
Instruction Decoder
Program Counter
The function of program counter (PC) holds
Temporary
Address for Memory
memory Operand
Address of Instruction
Which of the following is not a form of memory ?
Instruction Cache
Instruction Register
Instruction Opcode
Both (A) and (B)
Which of the following is not a form of memory ?
Instruction Cache
Instruction Register
Instruction Opcode
Both (A) and (B)
A dynamic RAM consists of
6 Transistors
2 Transistors and 2 Capacitors
1 Transistor and 1 capacitor
None of These
Four memory chips of 16 x 4 size have their address bases connected together. The system will be of size
64 X 64
16 X 16
32 X 16
256 X 1
The stack pointer in the microprocessor is a ______
16 bit register that points to stack memory locations
32 bit accumulator
memory location in the stack
flag regsiter used for the stack
