WorksheetsY12 December PPE Preparation
Total questions: 45
Worksheet time: 17mins
When main memory is divided into fixed / physical units.
Paging
Segmentation
Defragmentation
Pipelining
When main memory is divided logically into variable sizes according to its contents.
Paging
Segmentation
Defragmentation
Pipelining
Another term for 'main memory'.
Secondary storage
RAM
ROM
BIOS
What controls the content of the RAM?
The firewall
The application currently being used
The operating system
The ROM
Operating systems can run more than one program at a time. This process is known as (a) .
Which code will convert the integer variable i into text?
int(i)
i(txt)
str(i)
txt(i)
Which code will convert the text variable t into an integer number?
int(t)
t(txt)
str(t)
num(t)
Which data type would be most suitable for storing a count of the number of cars in a car park?
int
float
string
Boolean
Which data type would be most suitable for storing a calculated mean average of heights of children in a class?
int
float
string
Boolean
Which data type would be most suitable for storing the username of a player in a computer game?
int
float
string
Boolean
Which data type would be most suitable for recording whether a door is open or not?
int
float
string
Boolean
(a) is when the CPU executes one instruction whilst the next instruction is being decoded and the instruction after that is being fetched.
An (a) is a signal to the processor to a process or event needs immediate attention,
During the fetch part of the cycle, the contents of the (a) , which holds the address of the next instruction to be executed, is placed into the MAR.
During the (a) part of the FDE cycle, the contents of the program counter, which holds the address of the next instruction to be executed, is placed into the MAR.
In which stage of the FDE cycle is the contents of the program counter is increased by 1?
Fetch
Decode
Execute
In the (a) part of the cycle, the control unit works out what the instruction is and sends signals to coordinate the other components.
In the decode part of the cycle, the (a) works out what the instruction is and sends signals to coordinate the other components.
In the Decode stage of the FDE cycle, the instruction is split into an opcode and an (a) .
This is the command that the computer will carry out.
Opcode
Operand
An address in RAM where data will be read from or written to.
Opcode
Operand
Which of these processes does NOT happen during the execute stage of the FDE cycle?
The operand is copied to the MAR.
Data is fetched from RAM and passed up the data bus to the MDR.
An instruction is passed to the Accumulator.
The Control Unit sends out a memory read signal.
These processors can do complex operations, which can be carried out in just one instruction.
CISC
RISC
These processors have a wide range of instructions that can be used.
CISC
RISC
Which processor architecture allows instruction sets to accomplish tasks in fewer lines of assembly language?
CISC
RISC
Which processor architecture sees each instruction take one clock cycle?
CISC
RISC
Which processor architecture requires more RAM to store machine code instructions?
CISC
RISC
Which processor architecture is efficient as it enables pipelining to happen as instructions all take the same time to complete?
CISC
RISC
Accessing (a) is quicker than accessing RAM.
Holds the address of the memory location from which data (or an instruction) is to be fetched from or written to.
Memory Address Register
Memory Data Register
Current Instruction Register
Program counter
Used to temporarily store the data read from or written to memory.
Memory Address Register
Memory Data Register
Current Instruction Register
Program counter
Consists of 8, 16, 32 or 64 separate lines.
Data bus
Address bus
Control bus
Provides a bi-directional path for moving data and instructions between system components.
Data bus
Address bus
Control bus
Transmits memory addresses of 'words' (units of memory) that are used as operands in program instructions.
Data bus
Address bus
Control bus
Transmits command, timing and status information between system components.
Data bus
Address bus
Control bus
In which processor type is the same data bus used to transfer both data and instructions?
von Neumann
Harvard
In which processor type are two clock cycles are required to execute single instruction?
von Neumann
Harvard
In which processor type can the CPU access instructions and read/write at the same time?
von Neumann
Harvard
In which processor type is just one clock cycle required to execute a single instruction?
von Neumann
Harvard
In which processor type is there one single Control Unit?
von Neumann
Harvard
Breaking down a problem into smaller, solvable chunks.
Abstraction
Decomposition
Concurrent thinking
Removal of detail not needed to solve a problem.
Abstraction
Decomposition
Concurrent thinking
Which visualisation method allows cycles?
tree
graph
Which visualisation method start with a root node and has a hierarchy?
tree
graph
Which visualisation method has nodes classed as children and parents?
tree
graph
