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WorksheetsEC8552_ CAO_MODEL IV_PART B _ 09-12-2020
Total questions: 15
Worksheet time: 15mins
Name
Class
Date
1.
The number of instructions needed to add a numbers and store the result in memory using only one address instruction is ?
a)
n
b)
n-1
c)
n+1
d)
Independent of n
2.
Computers use addressing mode techniques for _____________________?
a)
giving programming versatility to the user by providing facilities as pointers to memory counters for loop control
b)
to reduce no. of bits in the field of instruction
c)
specifying rules for modifying or interpreting address field of the instruction
d)
All the above
3.
The push and pop instructions belonging to the category of transfer instructions of microprocessor perform data transformation between _______?
a)
two registers
b)
processor register and memory stack
c)
processor register and interface register
d)
interface register and memory word
4.
What will be the value obtained after multiplication of (-2) * (-3) using Booth’s Algorithm?
a)
6
b)
-6
c)
-5
d)
5
5.
The subtraction using 1’s complement of 110 – 100 will give the result ___________
a)
-11
b)
11
c)
10
d)
-10
6.
If you are given a word of size n bits, the range of 2’s complement of binary numbers is ________
a)
-2^(n+1) to +2^(n+1)
b)
-2^(n-1) to +2^(n-1)
c)
-2^(n-1) to +2^(n+1)
d)
-2^(n-1) to +2^(n-1)-1
7.
Assume that processor has a 1 ns clock cycle and that it uses 4 cycles for ALU operationsand branches and 5 cycles for memory and the relative frequencies of these operations are 40%, 20%, and 40%, respectively, then the average instruction execution time on the unpipelined processor is
a)
4.4 ns
b)
4.2 ns
c)
3.4 ns
d)
3.2 ns
8.
Register $2 written by subtraction can be written in the instruction
a)
sub $4, $1,$3
b)
sub $2, $1,$3
c)
add $2, $1,$3
d)
mul $2, $1,$3
9.
The given set of instructions add $s0, $t0, $t1; sub $t2, $s0, $t3; shows the
a)
Structural hazards
b)
Data hazards
c)
Forwading bypassing
d)
Pipeline stall
10.
Average access time of memory for having memory-hierarchy performance is given as?
a)
Average memory access time = Hit time + Miss rate
b)
Average memory access time = Hit time + Miss rate
c)
Average memory access time = Hit time + Miss rate + Miss penalty
d)
Average memory access time = Hit time + Miss rate - Miss penalty
11.
Consider the data from above question. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?
a)
222 nanoseconds
b)
888 nanoseconds
c)
902 nanoseconds
d)
968 nanoseconds
12.
The cache memory of 1K words uses direct mapping with a block size of 4 words. How many blocks can the cache accommodate?
a)
256 words
b)
512 words
c)
1024 words
d)
128 words
13.
In which procedure of dynamic algorithm, the priority line is connected from the priority-out of the last device back to the priority-in of the first device in a closed loop?
a)
(A) Time slice
b)
(B) Rotating daisy-chain
c)
(C) Polling
d)
(D) LRU
14.
A ____________WAN can be developed using leased private lines or any other transmission facility
a)
Hybrids
b)
B peer-to-peer
c)
C Two-tiered
d)
D Three-tiered
15.
Data communication system spanning states, countries, or the whole world is ________
a)
LAN
b)
B WAN
c)
C MAN
d)
D None of the mentioned
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