Clock frequency is 1GHz. The given counter is down counter. The initial count Q2Q1Q0 is '111'. After 15 positive edges what will be the counter output

A Ring oscillator consists of 7 inverters is running at frequency of 1MHz. The propagation delay per gate is _____ microsec. (Note: output is taking at the 7th Inverter only).

Number of 1s in the sequence of XNOR gate output for 12 clock pulses. Initially Q1Q2Q3 is '000'. (Q3 is MSB and Q1 is LSB)

Initially Q1Q2 are '00' and D1, Y (output of NAND gate) are '1'. For 5 clock cycles the number of 1s in the Y (output of NAND gate) sequence?

Clock frequency is 1GHz. This is MOD-n counter find n value and mention the MOD-n counter output signal frequency.

A 4-bit shift register circuit configured for right shift operation Din->A, A->B, B->C, C->D. If present state of shift register ABCD = 1101, number of clock cycles required to reach ABCD=1100

Initially loaded with 1010. Subsequently shift register is clocked and with each clock pulse the pattern gets shifted by one bit position to right. With each shift, the bit at serial input is pushed to left most position(MSB). After how many clock pulses will ocntent of shift register becomes 0101.

Are synchronous faster than ripple counters?

(True/False)

This is mod K counter, What is K?

Resultant flip flop after connecting XNOR gate to D flip flop?

A 4 bit modulo 16 ripple counter uses JK flip flops. If propagation delay of each flip flop is 25ns. The max clock frequency that can be used is(Hint: max clock frequency is when worst case delay occurs).

12. Output frequency for a frequency division circuit that contains 16 flip-flops with an input clock frequency of 393.216 MHz.

Which type of counter is it?

An 16-bit serial in/serial out shift register is used with a clock frequency of 250 kHz. What is the time delay between the serial input and the Q4 output?

Consider the given circuit, race around condition

When the output of NAND gate in circuit is 0, it implies that data has

Consider a 4 bit Johnson counter with an initial value of 0001. The counting sequence of this counter is:

In the given figure, the initial sequence is 0001 for QA, QB, QC, QD respectively and there is no delay for the flipflops and xor gates.

What is the sequence after four clock pulses?

Consider the circuit which is given input as '1' for J and K for 3 flipflops(Active low asynchronous reset). It works as