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WorksheetsEC8095_VLSI DESIGN_IAT2_PART B
Total questions: 15
Worksheet time: 30mins
Name
Class
Date
1.
1.If an inverter has a power supply 1v, dynamic power 10watt,and load capacitance of 1F then the frerquency at which inverter being switched will be (CO2)(B3)
a)
0.1Hz
b)
1Hz
c)
10Hz
d)
100Hz
2.
2. If p=1watt,f=2Hz and C=5F then VDD will be (CO2)(B3)
a)
0.1
b)
0.3
c)
0.5
d)
1
3.
3.The MOSFETS are arranged in this configuration to provide __________(CO2)(B2)
a)
Zero static power dissipation
b)
High Input impedance
c)
Both zero static power dissipation and high input impedance
d)
None of the mentioned
4.
4.The power dissipation in Pseudo-nMOS is reduced to about ________ compared to nMOS device.(CO2)(B2)
a)
50
b)
30
c)
60
d)
20
5.
5.Which must be given the highest priority in design process?(CO2)(B2)
a)
architecture
b)
communication
c)
colour
d)
thickness
6.
6.Non inverting dynamic register storage cell consists of _________ transistors for nMOS and _________ for CMOS.(CO3)(B2)
a)
six, eight
b)
eight, six
c)
five, six
d)
six, five
7.
7. Sense amplifier closely resembles the active load (CO3)(B2)
a)
BJT differential amplifier
b)
MOSFETdifferential amplifier
c)
BICMOS differential amplifier
d)
FETdifferential amplifier
8.
8.To increase the speed of memory access in pipelining, we make use of _______(CO2)(B3)
a)
Special memory locations
b)
Special purpose registers
c)
Cache
d)
Buffers
9.
9.The output of sequential circuit is regarded as a function of time sequence of __________. A. Inputs B. Outputs C. Internal States D. External States (CO3)(B3)
a)
A & D
b)
A & D
c)
A & D
d)
A & D
10.
10. Before the commencement of design, the clocking strategy determine/s _________(CO3)(B2)
a)
Number of clock signals necessary for routing throughout the chip
b)
Number of transistors used per storage requirement
c)
Power dissipated by chip & the size of chip
d)
All of the above
11.
11.Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points?(CO3)(B2)
a)
H tree
b)
Balanced tree clock network
c)
Both a and b
d)
None of the above
12.
12.Timing analysis is more efficient with synchronous systems whose maximum operating frequency is evaluated by the _________path delay between consecutive flip-flops.(CO3)(B3)
a)
shortest
b)
average
c)
longest
d)
unpredictable
13.
13.In MOS switch, clock feedthrough effect is also known as __________.A. charge injection B. charge feedthrough C. charge carrier D. charge ejaculation(CO3)(B2)
a)
A & B
b)
B & C
c)
C & D
d)
B & D
14.
14.When a clock signal is gated with another signal like load signal, output is not affected.(CO3)(B1)
a)
true
b)
false
15.
15.In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value.(CO3)(B3)
a)
Highest
b)
Average
c)
Lowest
d)
None of the above
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