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Design of Digital ICs

Total questions: 87

Worksheet time: 44mins

Name
Class
Date
1.

Among the given ICs technology, which one have the highest number of transistors per chip?

a)

MSI

b)

LSI

c)

SSI

d)

VLSI

2.

Range of transistors per package in LSI technology

a)

50 to < 100

b)

<10

c)

10 to <500

d)

500 to <20K

3.

Range of transistors per package in VLSI technology

a)

10 to <500

b)

20K to <100k

c)

>1 M

d)

100k to <1M

4.

The output of an exclusive-NOR gate is 1,Which input combination is correct?

a)

A = 1 B = 0

b)

A = 0 B = 1

c)

A = 0 B = 0

d)

none of the above

5.

OR gate with schematic "bubbles" on its inputs performs the same functions as___gate.

a)

NOT

b)

EX-OR

c)

NAND

d)

NOR

6.

Which of the following combinations cannot be combined into K-map groups?

a)

Corners in the same row

b)

Corners in the same column

c)

Diagonal corners

d)

Overlapping combinations

7.

Which of the following memories uses one transistor and one capacitor as basic memory unit?

a)

SRAM

b)

DRAM

c)

Both

d)

None

8.

Which logic family provide minimum power dissipation

a)

TTL

b)

CMOS

c)

ECL

d)

JFET

9.

How many input and output required for multiplexer ?

a)

Many input and one output

b)

One input and many output

c)

One input and one output

d)

None of the above

10.

If 4 input MUXes drive a 4 input multiplexer, it results a

a)

16 input MUX

b)

8 input MUX

c)

6 input MUX

d)

4 input MUX

11.

What is the expansion of VLSI

a)

Very Long Scale Integration

b)

Very Long Scale IC

c)

Very Large Scale Integration

d)

Very Large Scale ic

12.

Expansion of MOS is

a)

Metal Oxide Silicon

b)

Metal Oxide Semiconductor

c)

Metal Oxide Silicondiode

d)

Metal oxide Signboard

13.

In NMOS transistor, when voltage applied to gate is '1' logic , the transistor acts like

a)

open switch

b)

closed switch

c)

gets burnt

d)

nothing happens

14.

The logic gate whose output is '1' when one of the inputs is '1' is called

a)

AND gate

b)

OR gate

c)

XOR gate

d)

XNOR gate

15.

The logic gate in which output ='1' when both inputs are different is called

a)

AND gate

b)

OR gate

c)

XOR gate

d)

XNOR gate

16.

In this circuit, when inputs a=0, b=1, what is the output 

a)

1

b)

0

c)

High impedance 

d)

Shortcircuit

17.

PMOS transistor is used to pass

a)

0

b)

1

c)

infinity

d)

any information

18.

 f= x.y‾f=\ \overline{x.y}    This function represents

a)

AND gate

b)

NAND gate

c)

OR gate

d)

NOR gate

19.

In enhancement mode, device is in _________ condition.


a)

a) conducting

b)

b) non conducting

c)

c) partially conducting

d)

d) insulating

20.

MOS transistor structure is ____________


a)

a) symmetrical

b)

b) non symmetrical

c)

c) semi symmetrical

d)

d) pseudo symmetrical

21.

In MOS transistors _______________ is used for their gate.

a)

a) metal

b)

b) silicon-di-oxide

c)

c) polysilicon

d)

d) gallium

22.

Enhancement mode device acts as ____ switch, depletion mode acts as _____ switch.


a)

a) open, closed

b)

b) closed, open

c)

c) open, open

d)

d) close, close

23.

Inversion layer in n channel enhancement mode consists of excess of ____________

a)

a) positive carriers

b)

b) negative carriers

c)

c) both in equal quantity

d)

d) neutral carriers

24.

What is Application Specific Integrated Circuit (ASIC)?

a)

is designed to fit a specific application

b)

a general purpose IC

c)

a very complex design

25.

In a MOS transistor, channel width has increased by 2 times. Corresponding change in the resistivity is,

a)

4 Times increase

b)

Doubled

c)

Reduced by half

d)

None of these

26.

The NMOS circuit chain shown in the figure can act as a

a)

Buffer

b)

NAND Gate

c)

NOR Gate

d)

Invertor

27.

The fastest logic family is

a)

CMOS

b)

NMOS

c)

TTL

d)

ECL

28.

Supply voltage of a CMOS circuit is doubled. Its dynamic power dissipation will

a)

not change

b)

be doubled

c)

be halved

d)

increase by 4 times

29.

In depletion mode, source and drain are connected by ____________


a)

a) depletion layer

b)

b) conducting channel

c)

c) Vdd

d)

d) Vss

30.
The n-type region created near the surface by the positive gate bias is called the inversion layer, and this condition is called ___________________.
a)
Channel inversion
b)
accumulation
c)
Surface inversion
d)
depletion
31.
The substrate bias coefficient is __________ in nMOS, ___________ in pMOS.
a)
negative, positive
b)
positive, negative
c)
positive, positive
d)
negative, negative
32.

the threshold voltage of an enhancement-type n-channel MOSFET is a _________ quantity, whereas the threshold voltage of a p-channel MOSFET is___________.

a)

positive, negative

b)

negative, positive

c)

negative, negative

d)

positive, positive

33.

for VDS = VDSAT, the inversion charge at the drain is reduced to zero, which is called the _____________ point

a)

Saturation

b)

Linear

c)

Cut-off

d)

pinch-off

34.

Source in nMOS transistors is doped with ______ material

a)

n-type

b)

p-type

c)

n & p type

d)

none of the mentioned

35.
In linear region, ______ channel exists
a)
uniform
b)
non-uniform
c)
wide
d)
uniform and wide
36.
Increasing Vsb, _______ the threshold voltage
a)
does not effect
b)
decreases
c)
increases
d)
exponentially increases
37.
According to body effect, substrate is biased with respect to
a)
source
b)
drain
c)
gate
d)
Vss
38.

In CMOS logic circuit the n-MOS transistor acts as:

a)

Load

b)

Pull up network

c)

Pull down network

d)

Not used in CMOS circuits

39.
In CMOS logic circuit the p-MOS transistor acts as:
a)
Pull down network
b)
Pull up network
c)
driver
d)
Short to ground
40.
In the CMOS inverter the output voltage is measured across:
a)
Drain of n-MOS transistor and ground
b)
Source of p-MOS transistor and ground
c)
Source of n-MOS transistor and source of p-MOS transistor
d)
Gate of p-MOS transistor and Gate of n-MOS transistor
41.

Which among the following is a combinational circuit

a)

Flip Flop

b)

Latch

c)

Counter

d)

Encoder

42.

The combinational circuit used for routing the input value to the output line based on the select signal combination

a)

Multiplexer

b)

Demultiplexer

c)

Encoder

d)

Decoder

43.

In synchronous counters all the flip flops are clocked at the same time

a)

True

b)

False

44.

Which among the following gates is an inequality detector

a)

XOR Gate

b)

XNOR Gate

c)

NAND Gate

d)

NOR Gate

45.

Flip flops are edge triggered and latches are level triggered

a)

True

b)

False

46.

Combinational digital circuits are capable of storing atleast one bit of data

a)

True

b)

False

c)

Depends on the design

d)

Cannot be determined

47.

Which logic family provide minimum power dissipation

a)

TTL

b)

CMOS

c)

ECL

d)

JFET

48.

How many input and output required for multiplexer ?

a)

Many input and one output

b)

One input and many output

c)

One input and one output

d)

None of the above

49.

Silicon is extracted from

a)

Sand

b)

Clay

c)

Sea water

d)

Rocks

50.

CMOS inverter has ______ output impedance

a)

Low

b)

High

51.

Input resistance of CMOS inverter is

a)

High

b)

Low

52.

The effective Channel Length of a MOSFET in saturation decreases with increase in

a)

Gate voltage

b)

Source Voltage

c)

Drain Voltage

d)

Body Voltage

53.

In MOSFET operating in saturation region, the channel length modulation effect causes

a)

An increase in gate source capacitance

b)

A decrease in Trans conductance

c)

A decrease in unity gain bandwidth product

d)

A decrease in output resistance

54.

In MOSFET devices the N-channel type is better than the P – Channel type in the following respects.

a)

It has better immunity

b)

It is faster

c)

It is TTL compatible

d)

It has better drive capability

55.

When the channel pinches off in nmos?

a)

Vgs>Vds

b)

Vds>Vgs

c)

Vds>(Vgs-Vth)

d)

Vgs>(Vds-Vth)

56.

------------------- can pass a logic 1 perfectly, but cannot pass a logic 0 perfectly

a)

nmos

b)

Transmission gate

c)

pmos

d)

keepers

57.
PMOS transistors always passes ____________ (CO1)(B3)
a)
Strong 1
b)
moderate 0
c)
strong 0
d)
weak 1
58.
NMOS transistors always passes ____________ (CO1)(B3)
a)
Strong 1
b)
moderate 0
c)
strong 0
d)
weak 0
59.
when Vsb is applied between source s and body b, it increases the amount of charge required to invert the channel, hence it increases threshold voltage Vt. This effect is called ____________ (CO1)(B4)
a)
Body effect
b)
threshold voltage effect
c)
junction leakage effect
d)
none of these
60.
In MOS transistor, when Vgs>Vt and Vds> Vdsat, then the channel becomes ____________(CO1)(B3)
a)
inverted
b)
Pinches off
c)
straight
d)
formed
61.
In pseudo NMOS logic, the pull up network consists of ___________ (CO2)(B4)
a)
N Pmos transistors
b)
only one PMOS
c)
N+1 PMOS transistors
d)
none of these
62.

A device which inverts its input is a/an __________.

a)

A. inverter

b)

B. logic gate

c)

C. chip

63.

Noise margin NML is

a)

VOH- VIL

b)

VOL- VIH

c)

VOL- VIL

d)

VIL- VOL

64.

VIH means

a)

maximum HIGH input voltage

b)

minimum HIGH input voltage

c)

maximum HIGH output voltage

d)

maximum LOW input voltage

65.

Lithography is

a)

Process used to transfer a pattern to a layer on the chip

b)

Process used to develop an oxidation layer on the chip

c)

Process used to develop a metal layer on the chip

d)

Process used to produce the chip

66.

Silicon oxide is patterned on a substrate using

a)

Physical lithography

b)

Photolithography

c)

Chemical lithography

d)

Mechanical lithography

67.

What are the three terminals in a FET transistor?

a)

gate, source, drain

b)

base, emitter, collector

c)

gate, base, drain

d)

source, drain, collector

68.
How are metal oxides formed?
a)
When metals react with oxide.
b)
When metals react with water.
c)
When metals react with air.
d)
When metals react with oxygen.
69.
3. Which of the following is a pentavalent impuity added while forming an extrinsic semiconductor ?
a)
(a) Boron 
b)
Arsenic
c)
Indium
d)
Gallium
70.

Doping of Semiconductors

a)

materials which can conduct electricity better than insulator, but not as well as conductors.

b)

The process of adding of a certain amount of specific impurities atoms in the pure semiconductor.

c)

when 4 electrons in outermost orbit.

71.

The process of adding an impurity to an intrinsic semiconductor is called

a)

Doping

b)

Ionization

c)

Recombination

d)

Atomic modification

72.

During formation of p-n junction

a)

an electron diffuses from n to p side

b)

a hole diffuses from p to n side

c)

a hole diffuses from n to p side

d)

an electron diffuses from p to n side

73.

Which of the following terminals does not belong to the MOSFET?

a)

Drain

b)

Gate

c)

Base

d)

Source

74.

Choose the correct statement

a)

MOSFET is a unipolar, voltage controlled, two terminal device

b)

MOSFET is a bipolar, current controlled, three terminal device

c)

MOSFET is a unipolar, voltage controlled, three terminal device

d)

MOSFET is a bipolar, current controlled, two terminal device

75.

The output characteristics of a MOSFET, is a plot of

a)

Id as a function of Vgs with Vds as a parameter

b)

Id as a function of Vds with Vgs as a parameter

c)

Ig as a function of Vgs with Vds as a parameter

d)

Ig as a function of Vds with Vgs as a parameter

76.

MOSFET is also known as….

a)

IGBJT

b)

IGFET

c)

IGBET

d)

None

77.

Minimum delay before any output starts to change once input changes

a)

Propagation delay

b)

Contamination delay

78.

Sequential circuit includes

a)

only Delays

b)

Only Feed backs

c)

Delays and Feed backs from input to output

d)

Delays and Feed backs from output to input

79.

The interval after the clock where the data must be held stable

a)

Setup time

b)

Hold time

80.

Which is the delay elements for clocked system?

a)

AND gates

b)

OR gates

c)

Flip flops

d)

Multiplexers

81.

Maximum delay after which all outputs are stable once input changes

a)

Propagation delay

b)

contamination delay

82.

The interval before the clock where the data must be held stable

a)

Setup time

b)

Hold time

83.

Clocked sequential circuits are

a)

two phase overlapping clock

b)

two phase non overlapping clock

c)

four phase overlapping clock

d)

four phase non overlapping clock

84.

Latches and Flip flops are the examples of …………………. Logic circuits

a)

Combinational

b)

Sequential

85.

Number of inputs for D flip flop

a)

3

b)

2

c)

1

86.

The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called

a)

Combinational Circuits

b)

Sequential Circuits

c)

None of the above

87.

Combinational circuit has

a)

memory and depend only on the present input.

b)

no memory and depend only on the present input.

c)

no memory and depends on past and future inputs.

d)

memory and does not depend on present input.

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