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WorksheetsDLCOA_Quiz1_SH2021
Total questions: 18
Worksheet time: 10mins
Name
Class
Date
1.
Your Name
4 lines
2.
Your Division
a)
SE3
b)
SE4
c)
SE9
3.
Your Roll No.
4 lines
4.
Which of the following is termed as minimum error code.
a)
Gray Code
b)
Octal Code
c)
Excess-3 Code
d)
Binary Code
5.
Let ∗ be defined as x∗y=x'+y, Let z=x∗y. Value of z∗x is
a)
x'+y
b)
x
c)
0
d)
1
6.
Zero has two representations in:
a)
Sign Magnitude
b)
1's Complement
c)
2's Complement
d)
Both a & b
7.
Process of writing to PROM is called burning because
a)
The cells burn due to the charge
b)
The fuse burns due to the charge
8.
EEPROM can write 512 bytes at a time
a)
true
b)
Flase
9.
Precharge is used close an open row and to bring the SDRAM to idle state.
a)
true
b)
Flase
10.
The 2′s complement representation of (−539) in hexadecimal is
a)
ABE
b)
DBC
c)
DE5
d)
9 E7
11.
AND Gate EXOR Gate combination is
a)
Full Adder
b)
Half Adder
c)
Flip Flop
d)
Both half adder and full adder
12.
__________ consists essentially of internal flip-flops that store the binary information.
a)
Static RAM
b)
Dynamic RAM
c)
PROM
d)
EEPROM
13.
If A, B and C are the inputs of a full adder then the carry is given by __________
a)
A AND B OR (A OR B) AND C
b)
(A AND B) OR (A AND B)C
c)
A OR B OR (A AND B) C
d)
A XOR B XOR (A XOR B) AND C
14.
If x denotes the number of memory locations and y denotes the word size, then an expression that denotes the storage capacity is ______________
a)
x*y
b)
2^x
c)
x+y
d)
x^2
15.
4bit Gray Code for deimal number 9 is:
a)
1101
b)
1011
c)
1001
d)
101
16.
In ____________ mapping, the data can be mapped in one of the blocks of a givet set in the Cache Memory.
a)
Associative
b)
Direct
c)
Set Associative
d)
Indirect
17.
The amount of ROM needed to implement a 4 bit multiplier is
a)
64 bit
b)
128 bit
c)
1 Kb
d)
2Kb
18.
In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?
a)
A smaller block size implies better spatial locality
b)
A smaller block size implies a smaller cache tag and hence lower cache tag overhead
c)
A smaller block size incurs a lower cache miss penalty
d)
A smaller block size implies a larger cache tag and hence lower cache hit time
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