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WorksheetsEEE1001-Quiz2
Total questions: 10
Worksheet time: 11mins
Which of the following logic expressions represents the logic diagram shown?
X=AB’+A’B
X=(AB)’+AB
X=(AB)’+A’B’
X=A’B’+AB
The device shown here is most likely a ________
Comparator
Multiplexer
Demultiplexer
Decoder
For the output F to be 1 in the logic circuit shown, the input combinations should be
A = 0, B = 1, C = 0
A = 1, B = 1, C = 1
A = 0, B = 0, C = 1
All of the above
Which is the major functioning responsibility of the multiplexing combinational circuit?
Decoding the binary information
Generation of all minterms in an output function with OR-gate
Generation of selected path between multiple sources and a single destination
Encoding of binary information
The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?
0, B
0, A
1, B
1, A
If half adders and full adders are implemented using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be
1,16
16,1
8,8
17,0
The largest two digit hexadecimal number is
(FE)
(FD)
FF
EF
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
Low input voltages
Synchronous operation
Gate impedance
Cross coupling
Whose operations are more faster among the following?
Combinational circuits
Sequential circuits
Latches
Flip-flops
Which of the following is correct for a gated D flip-flop?
The output toggles if one of the inputs is held HIGH
Only one of the inputs can be HIGH at a time
The output complement follows the input when enabled
Q output follows the input D when the enable is HIGH
