Free Printable Verilog HDL

1.

Modules written in verilog can represent a design

a)

At the behavioral level

b)

At the dataflow level

c)

At the switch level

d)

All of these

2.

Operator which precedes the operand

a)

Unary

b)

Binary

c)

Ternary

d)

None

3.

Which is legal negative number

a)

4'd-3

b)

6'-d3

c)

-6d'3

d)

None

4.

What is the default value for reg data type

a)

0

b)

1

c)

z

d)

x

5.

Turn off delay means, gate output transition to

a)

0

b)

1

c)

z

d)

x

6.

What is system task to suspend simulation

a)

$finish

b)

$monitor

c)

$display

d)

$stop

7.

Parameter value can be overridden at module instance by

a)

Specparam

b)

Defparam

c)

Parameter

d)

None

8.

In continuous assignment left hand side must be

a)

net

b)

reg

c)

scalar or vetor net

d)

scalar or vector reg

9.

10 % 3 evaluates to

a)

-1

b)

1

c)

0

d)

x

10.

What are the possible values of == operator

a)

0,1

b)

0,x

c)

1,x

d)

0,1,x

11.

What is the time period of clock #10 clock = ~clock

a)

10

b)

20

c)

.05

d)

.1

12.

If x=4'b1100 then x<<2 is

a)

4'b1000

b)

4'b0000

c)

4'b0011

d)

4'b0110

13.

If A=1'b1,B=2'b01,C=2'b00 then Y= {A,B[0],C[1]} equals

a)

3'b110

b)

3'b100

c)

3'b101

d)

3'b000

14.

wait statement is

a)

edge sensitive bit

b)

level sensitive

c)

both

d)

none

15.

<= is used in

a)

Blocking

b)

Non Blocking

c)

Both

d)

None

16.

Asynchronous reset is

a)

Clock dependent

b)

Clock independent

c)

Either

d)

None

17.

For describing circuits like flip flops _____________ statement is used

a)

always

b)

assign

c)

initial

d)

forever

18.

Which construct is used to execute loop fixed number of times

a)

while

b)

forever

c)

for

d)

none

19.

Inout ports must always be

a)

net

b)

reg

c)

trireg

d)

none

20.

RTL stands for _____________.

a)

resistor‐transfer logic

b)

register‐transistor logic

c)

register‐transfer logic

d)

none of these

Verilog HDL

Total questions: 20

Worksheet time: 10mins

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