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Computer Architecture - I/O moethods

Total questions: 40

Worksheet time: 20mins

Name
Class
Date
1.

The method which offers higher speeds of I/O transfers is ___________

a)

Interrupts

b)

Memory mapping

c)

Program-controlled I/O

d)

DMA

2.

In memory-mapped I/O ____________

a)

The I/O devices have a separate address space

b)

The I/O devices and the memory share the same address space

c)

A part of the memory is specifically set aside for the I/O operation

d)

The memory and I/O devices have an associated address space

3.

The input and output operations are respectively similar to the operations,

a)

read, read

b)

write, write

c)

read, write

d)

write, read

4.

In memory-mapped scheme, the devices are viewed as

a)

distinct I/O devices

b)

memory locations

c)

only input devices

d)

only output devices

5.

In the keyboard Monitor interface, the text code named International Reference Alphabet (IRA) is used represent each character using how many bits

a)

7

b)

8

c)

9

d)

10

6.

In International Reference Alphabet ___________ is an example to printable character.

a)

Alphabet

b)

ESC

c)

F1

d)

Enter

7.

In International Reference Alphabet ____________ is an example to control character

a)

Alphabet

b)

Numbers

c)

Special characters

d)

ESC

8.

Which functionality of the I/O module coordinates the traffic flow between resources inside the processor and external resources?

a)

Control and Timing

b)

Device Communication

c)

Data buffering

d)

Error Detection

9.

Which functionality of the I/O module coordinates in temporarily holding the data between being transferred between the I/O module and external devices.

a)

Control and Timing

b)

Device Communication

c)

Data buffering

d)

Error Detection

10.

The I/O modules use ___________ lines to issue commands to the I/O module.

a)

Control

b)

Data

c)

Address

d)

Information

11.

The data transferred to and from the module are buffered in one or more ___________ register.

a)

Data

b)

Address

c)

Status

d)

Cache

12.

Which I/O technique works without interrupt?

a)

Programmed I/O

b)

Interrupt Driven I/O

c)

DMA

d)

None

13.

In programmed I/O, the CPU stays in the program loop until the I/O unit indicates that it is ready for data transfer.

a)

True

b)

False

14.

Which I/O command is used to activate the peripheral and tell it what to do?

a)

Control

b)

Test

c)

Read

d)

Write

15.

Which I/O command is used to check various status conditions associated with the I/O module and its peripheral?

a)

Control

b)

Test

c)

Read

d)

Write

16.

Which I/O command is used by the I/O module to obtain an item of data from the peripheral and place it in an internal buffer?

a)

Control

b)

Test

c)

Read

d)

Write

17.

Which I/O command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral?

a)

Control

b)

Test

c)

Read

d)

Write

18.

Memory mapped I/O uses the same address bus to connect both primary memory and memory of hardware devices.

a)

True

b)

False

19.

Memory mapped I/O is less efficient than Isolated I/O.

a)

True

b)

False

20.

In interrupt driven I/O, the processor issues an I/O command to a module and then go on to do some other useful work.

a)

True

b)

false

21.

The process wherein the processor constantly checks the status flags is called as ___________

a)

Polling

b)

Inspection

c)

Reviewing

d)

Echoing

22.

In polling ____________

a)

Busy – wait cycle wait for I/O from device

b)

Interrupt handler receives interrupts

c)

Interrupt request line is triggered by I/O device

d)

All of the mentioned

23.

How does the software trigger an interrupt?

a)

Sending signals to CPU through bus

b)

Executing a special operation called system call

c)

Executing a special program called system program

d)

Executing a special program called interrupt trigger program

24.

What is ISR?

a)

Information Service Request

b)

Interrupt Service Request

c)

Interrupt Service Routine

d)

Information Service Routine

25.

How does the hardware trigger an interrupt?

a)

Sending signals to CPU through a system bus

b)

Executing a special operation called system call

c)

Executing a special program called system program

d)

Executing a special program called interrupt trigger program

26.

DMA is used for

a)

High Speed devices

b)

Low speed devices

c)

Utilizing CPU cycles

d)

All of the mentioned

27.

In an interrupt driven I/O ______________

a)

The CPU uses polling to watch the control bit constantly, looping to see if a device is ready

b)

The CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available

c)

The CPU receives an interrupt when the device is ready for the next byte

d)

The CPU runs a user written code and does accordingly

28.

In which interrupt drive I/O method the I/O devices are connected in cascade and the module is identified by the vector address.

a)

Software poll

b)

Daisy chain

c)

Bus arbitration

d)

None

29.

The DMA module is capable of mimicking the processor and, indeed, of taking over control of the system from the processor.

a)

True

b)

False

30.

Direct Memory Access involves transfer of data between I/O devices and memory by an external circuitry system called DMA ________ without involving the processor.

a)

Controller

b)

Instructor

c)

Moderator

d)

Processor

31.

In DMA control operation, the bus request line from the controller in connected with HOLD pin of the processor.

a)

True

b)

False

32.

In synchronous I/O data frames communicate with the constant time intervals between each frame remaining constant.

a)

True

b)

False

33.

The quickest DMA data transfer mode is

a)

Burst mode

b)

Cycle stealing mode

c)

Interleaving mode

d)

None

34.

Execution of several activities at the same time.

a)

Processing

b)

parallel processing

c)

serial processing

d)

multitasking

35.

___________ is the technique of decomposing a sequential tasks into sub-tasks with each sub-task being executed in a special dedicated stage that operate concurrently with each other.

a)

DMA

b)

Pipelining

c)

Vector Processing

d)

Interconnection network

36.

The method which offers higher speeds of I/O transfers is ___________

a)

Interrupts

b)

Memory mapping

c)

Program-controlled I/O

d)

DMA

37.

Which category includes traditional uniprocessors?

a)

SISD

b)

SIMD

c)

MISD

d)

MIMD

38.

The advantage of I/O mapped devices to memory mapped is ___________

a)

The I/O offers faster transfer of data

b)

The devices connected using I/O mapping have a bigger buffer space

c)

The devices have to deal with fewer address lines

d)

No advantage as such

39.

In memory mapped I/O, the external devices and memory unit share the ____________ space in memory.

a)

Same address space

b)

Different address space

c)

Associated

d)

Auxiliary

40.

In which communication the data is received or transmitted at constant time intervals with uniform phase differences?

a)

Synchronous I/O

b)

Asynchronous I/O

c)

Allochronic I/O

d)

Noncontemporary I/O