WorksheetsComputer Architecture - I/O moethods
Total questions: 40
Worksheet time: 20mins
The method which offers higher speeds of I/O transfers is ___________
Interrupts
Memory mapping
Program-controlled I/O
DMA
In memory-mapped I/O ____________
The I/O devices have a separate address space
The I/O devices and the memory share the same address space
A part of the memory is specifically set aside for the I/O operation
The memory and I/O devices have an associated address space
The input and output operations are respectively similar to the operations,
read, read
write, write
read, write
write, read
In memory-mapped scheme, the devices are viewed as
distinct I/O devices
memory locations
only input devices
only output devices
In the keyboard Monitor interface, the text code named International Reference Alphabet (IRA) is used represent each character using how many bits
7
8
9
10
In International Reference Alphabet ___________ is an example to printable character.
Alphabet
ESC
F1
Enter
In International Reference Alphabet ____________ is an example to control character
Alphabet
Numbers
Special characters
ESC
Which functionality of the I/O module coordinates the traffic flow between resources inside the processor and external resources?
Control and Timing
Device Communication
Data buffering
Error Detection
Which functionality of the I/O module coordinates in temporarily holding the data between being transferred between the I/O module and external devices.
Control and Timing
Device Communication
Data buffering
Error Detection
The I/O modules use ___________ lines to issue commands to the I/O module.
Control
Data
Address
Information
The data transferred to and from the module are buffered in one or more ___________ register.
Data
Address
Status
Cache
Which I/O technique works without interrupt?
Programmed I/O
Interrupt Driven I/O
DMA
None
In programmed I/O, the CPU stays in the program loop until the I/O unit indicates that it is ready for data transfer.
True
False
Which I/O command is used to activate the peripheral and tell it what to do?
Control
Test
Read
Write
Which I/O command is used to check various status conditions associated with the I/O module and its peripheral?
Control
Test
Read
Write
Which I/O command is used by the I/O module to obtain an item of data from the peripheral and place it in an internal buffer?
Control
Test
Read
Write
Which I/O command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral?
Control
Test
Read
Write
Memory mapped I/O uses the same address bus to connect both primary memory and memory of hardware devices.
True
False
Memory mapped I/O is less efficient than Isolated I/O.
True
False
In interrupt driven I/O, the processor issues an I/O command to a module and then go on to do some other useful work.
True
false
The process wherein the processor constantly checks the status flags is called as ___________
Polling
Inspection
Reviewing
Echoing
In polling ____________
Busy – wait cycle wait for I/O from device
Interrupt handler receives interrupts
Interrupt request line is triggered by I/O device
All of the mentioned
How does the software trigger an interrupt?
Sending signals to CPU through bus
Executing a special operation called system call
Executing a special program called system program
Executing a special program called interrupt trigger program
What is ISR?
Information Service Request
Interrupt Service Request
Interrupt Service Routine
Information Service Routine
How does the hardware trigger an interrupt?
Sending signals to CPU through a system bus
Executing a special operation called system call
Executing a special program called system program
Executing a special program called interrupt trigger program
DMA is used for
High Speed devices
Low speed devices
Utilizing CPU cycles
All of the mentioned
In an interrupt driven I/O ______________
The CPU uses polling to watch the control bit constantly, looping to see if a device is ready
The CPU writes one data byte to the data register and sets a bit in control register to show that a byte is available
The CPU receives an interrupt when the device is ready for the next byte
The CPU runs a user written code and does accordingly
In which interrupt drive I/O method the I/O devices are connected in cascade and the module is identified by the vector address.
Software poll
Daisy chain
Bus arbitration
None
The DMA module is capable of mimicking the processor and, indeed, of taking over control of the system from the processor.
True
False
Direct Memory Access involves transfer of data between I/O devices and memory by an external circuitry system called DMA ________ without involving the processor.
Controller
Instructor
Moderator
Processor
In DMA control operation, the bus request line from the controller in connected with HOLD pin of the processor.
True
False
In synchronous I/O data frames communicate with the constant time intervals between each frame remaining constant.
True
False
The quickest DMA data transfer mode is
Burst mode
Cycle stealing mode
Interleaving mode
None
Execution of several activities at the same time.
Processing
parallel processing
serial processing
multitasking
___________ is the technique of decomposing a sequential tasks into sub-tasks with each sub-task being executed in a special dedicated stage that operate concurrently with each other.
DMA
Pipelining
Vector Processing
Interconnection network
The method which offers higher speeds of I/O transfers is ___________
Interrupts
Memory mapping
Program-controlled I/O
DMA
Which category includes traditional uniprocessors?
SISD
SIMD
MISD
MIMD
The advantage of I/O mapped devices to memory mapped is ___________
The I/O offers faster transfer of data
The devices connected using I/O mapping have a bigger buffer space
The devices have to deal with fewer address lines
No advantage as such
In memory mapped I/O, the external devices and memory unit share the ____________ space in memory.
Same address space
Different address space
Associated
Auxiliary
In which communication the data is received or transmitted at constant time intervals with uniform phase differences?
Synchronous I/O
Asynchronous I/O
Allochronic I/O
Noncontemporary I/O
