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WorksheetsCOMPUTER ARCHITECTURE
Total questions: 15
Worksheet time: 8mins
EDSAC stands for
Electronic display storage automatic calculator
Electronic delay storage automatic calculator
Electronic delay storage automatic circuit
Electronic display automatic circuit
RAM is usually called
Logical Memory
Physical memory
Conceptual memory
Users Memory
control unit determines the address of the next instruction be executed and loads it into the program counter.
Instruction Interpretation
Instruction regulation
Instruction composition
Instruction sequencing
PSW stands for
Process status word
Program status word
Program status width
process status width
State True or False.
1. “MOVE Y, A” is a two address instruction.
2. “MUL T, D, E” is a three address instruction.
1-True, 2-False
1-False, 2-True
1-False, 2-False
1-True, 2-True
Tape units have ___ access.
Sequential
Random
Associative
Direct
Generally ___ is used to hold the data temporarily.
ROMs
EPROMs
Buffers
Magnetic disks
The following logic building block can be used to implement any combinational logic circuit
Ex-Or gate
Encoder
Multiplexer
Decoder
The simplified form of the expression AB+ABC’ is
AB
A(B+C)’
A(B+C)
None of these
A truth table of the n variables has … Minterms
N2
(n-1)2
2n-1
2n
In a six-stage pipeline assuming that there are no branch instructions. If we want to execute 15 instructions. What is the time required to execute these instructions?
15
20
21
19
Which type of data hazard is not possible?
WAR
WAW
RAR
RAW
Dynamic pipeline allows
.Only stream line connection
function to evaluate
Multiples functions to evaluate
To perform fixed function
The expression delayed load is used in the context of
Processor-printer communication
Memory-monitor communication
Pipelining
None of these
The instruction execution flow in the pipeline processor is represented by
Flow chart
Data flow diagram
Time space diagram
.Reservation table
