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Worksheets

VLSID Lab Monday Quizizz

Total questions: 11

Worksheet time: 8mins

Name
Class
Date
1.

What is the full form of VHDL?

a)

Verilog Hardware Description Language

b)

Very high speed Integrated circuit Hardware Description Language

c)

Variable Hardware Description Language

d)

Very High speed Description Language

2.

What is the basic use of EDA  (Electronic Design Automation) tools?

a)

Communication of Electronic devices

b)

Fabrication of Electronics hardware

c)

Electronic circuits simulation and synthesis

d)

Industrial automation

3.

A logic circuit that provides a HIGH output if one input or the other input HIGH, but not both, is HIGH, is an?

a)

Ex-OR gate

b)

Ex-NOR gate  

c)

NAND gate

d)

NOR gate

4.

How is an encoder different from a decoder?

a)

The output of an encoder is a binary code for 1-of-N input

b)

The output of a decoder is a binary code for N-of-1 output

c)

The output of a decoder is a binary code for 1-of-N input

d)

The output of an encoder is a binary code for N-of-1 output

5.

Which of the following is correct for a D latch?

a)

The output toggles if one of the inputs is held HIGH

b)

Only one of the inputs can be HIGH at a time

c)

The output complement follows the input when enabled

d)

Q output follows the input D when the enable is HIGH

6.

What is one disadvantage of the ripple-carry adder(full adder)?

a)

More stages are required to a full adder

b)

The interconnections are more complex

c)

All of the Mentioned

d)

It is slow due to propagation time

7.

A logic circuit that provides a HIGH output if one of input is HIGH, is an?

a)

NAND gate

b)

NOR gate

c)

Ex-OR gate

d)

Ex-NOR gate

8.

Which segments of a seven-segment LED should be lighted on to display the digit 1?

a)

Segments A and B

b)

Segments E and F

c)

Segments C and D

d)

Segments B and C

9.

Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which ___________

a)

Determine sign and magnitude

b)

Increase ripple delay

c)

Reduce propagation delay

d)

Add a 1 to complemented inputs

10.

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains

a)

00101

b)

00110

c)

01110

d)

00001

11.

Draw CMOS inverter