Memory Hierarchy pyramid?

a. CPU Register b.Cache Memory c. Primary Memory d. Secondary Memory e. Tertiary Memory

"Topic: ten advanced optimizations of cache performance"

Small and simple first-level caches and way prediction?

"Topic: ten advanced optimizations of cache performance"

Pipelined caches, multibanked caches and nonblocking caches.

"Topic: ten advanced optimizations of cache performance"

The critical word first and merging write buffers.

"Topic: ten advanced optimizations of cache performance"

Compiler optimizations.

_________ are a special class of DRAMs based on SDRAM designs but tailored for handling the higher bandwidth demands of graphic processing units.

______ is a type of EEPROM, which is normally read-only but can be erased.

A computer system is created using software on one physical computer in order to emulate the functionality of another separate physical computer.

______uses both hardware and software to enable a computer to compensate for physical memory shortages, temporarily transferring data from random access memory (RAM) to disk storage.

A _____ entry is like a cache entry where the tag holds portions of virtual address and the data portion holds a physical address, protection field, valid bit, and usually a use bit and a dirty bit