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WorksheetsBIM Peripherals Test
Total questions: 76
Worksheet time: 39mins
What does the CPU do?
Performs arithmetic and logic operations and controls the operation of the entire system.
True or false: Some tasks are completely controlled by the CPU, but for others it merely initiates as sequence of events which are controlled elsewhere, such as in a peripheral device.
What do peripheral devices do?
Permit communication of
information and storage of information.
True or false: Peripherals normally communicate through the CPU.
How many and what different types of peripherals are there in a computer?
The number and types of peripheral devices depend on the
main applications for which the computer system is
intended.
True or false: Excluding CPUs and
Memory all other
Input/Output devices
connected with the
computer systems are
altogether referred to
as peripheral devices
True or false: Modern computers perform operations very much faster than
most peripherals can generate or accept data.
True
False
Since it would be inappropriate to connect peripherals directly to the
CPU due to the CPU's speed, what do we do?
A Peripheral Adapter is
required to convert between the fast CPU and the slower peripherals
What are typically required functions performed after an address comparator matches an address?
Read from or write to a register (may be data
register) connected to a data bus.
What is a peripheral adaptor?
A device that works as an interface between
a fast CPU and a slow peripheral.
What is a data highway?
A data highway is a set of wires that moves different kinds of data around the computer.
What is a data bus?
A transporter of data that contains the information or program instructions
required by the CPU.
What is a good way to improve the speed of a data bus?
Add more data lines
Order data bus bit systems in order of fastest to slowest
32 bit, 16 bit, 8 bit
16 bit, 32 bit, 8 bit
8 bit, 16 bit, 32 bit
What does an address bus do?
The number of lines available for this determines the
maximum amount of physical memory that can be
addressed. What is the equation for the number of locations that can be addressed?
2^n
n^2
2 x n
n/2
What does a control bus do?
It contains control signals
Why are control signals necessary?
To maintain orderly flow of
data along the bus.
To indicate whether to read or write data during a transfer and timing signals
To indicate whether a transfer is to memory or a
peripheral adaptor.
To signal to the peripherals what is needed from the CPU.
Peripheral adaptors contain:
Control registers, status registers, and data registers
Control logic and address comparator
All of the mentioned
None of the mentioned
What is an address comparator?
It compares the address on the address bus with the peripheral
adapter’s address.
Why is an address comparator necessary?
To distinguish between adapters used for different
peripherals.
What happens if the address on the bus matches that of the adapter?
Then the control
lines are interpreted by the control logic to perform the required
function
What does a control register do?
Stores values written to it to control the operation of the
adaptor.
What does a status register do?
Can be read by the CPU to determine the status of the
device (e.g. whether it is ready for use, busy, switched
on/off etc.)
How many bits does each piece of information stored in the control and status registers need?
Generally only 1 bit. Such bits are stored in the control register and referred to as 'flags'.
What does a data register do?
Temporarily holds a value to be transferred to/from the peripheral so that it's not necessary to
synchronize the computer with the peripheral.
True or false: The transfer of data to or from the port can be done in two ways.
True
False
What are two ways to transfer data to or from the port?
Execute an instruction that causes a single byte or word to be
transferred.
Block Transfer (also called Direct Memory Access)
Be transferred via CPU register.
What is Block Transfer (also called Direct Memory Access)?
Executing a sequence of instructions that causes a special system
component associated with the interface to transfer a
sequence of bytes or words to/from a predesignated block of memory locations.
True or false: If Block Transfer takes place, data can only be transferred between memory and a port by a CPU register.
True
False
How is a stream of bytes or words able to be sent to memory from an I/O?
Successively input the byte or words one by one to the CPU and put them
in consecutive memory locations.This could be done with program loop.
Execute a sequence of instructions that causes a special system
component associated with the interface to transfer a
sequence of bytes or words to or from a predesignated block of memory locations.
What is a DMA controller?
A type of software that runs the data highways.
A special system
component associated with the interface that manages transferring
What precautions are taken in case of block transfer?
Take consecutive bytes or
words from memory and send them to external device.
The program would need
to successively, one by one, input the byte or words to the CPU and put them
in consecutive memory locations.
Supervision by the interface and the DMA
controller. Each byte is moved directly from port to the memory as soon as
it arrives at the port.
How is Block Transfer initiated?
The program need only give the required commands to
the interface and DMA controller
True or false: the interface and its DMA controller can take consecutive bytes or
words from memory and send them to external device.
Which of the following methods may be used to control the peripheral adaptor and pass data to
and from the attached peripheral?
Programmed I/O
Memory Mapped I/O
Interrupted I/O
DMA
General Input/output (I/O) operations
True or false: all transfers between the CPU and the peripheral adaptor are
completely under program control.
True
False
What kind of instructions does the processor contain?
Input data to the CPU from the peripheral
Output data from the CPU to the peripheral
Set individual bits in the peripheral adaptor's control register
Set individual bits in the peripheral adaptor's status register
instructions containing arithmetic, logic, and data movement
Intructions regarding reading, writing, and speaking
True or false: A program waits for the peripheral to be ready with data (or ready to receive
data) and then explicitly transfers the data
True
False
The CPU addresses the adapter and tests the status register. If the relevant bit
in the register shows that the peripheral is ready, what happens?
The CPU puts the data
into the interface unit transmit data register.
This will automatically set a flag to indicate that data is available for the peripheral.
What happens if the peripheral is not ready to recieve data?
The programmed I/O will wait and retry
True or false: The status of an input device may be tested and data taken from
the input data register if it is available
If an input device isn't ready to receive transported data and the I/O processor must wait and try again, what does this result in?
The processor sits idle waiting for the device for possibly significant
periods, when the time used up could have been filled with useful work.
For programmed I/O: What does the command "JZ" stand for?
If there are more than one device using programmed I/O, what happens?
It is necessary
to poll the ready bits of all the devices.
What is software polling?
The technique of testing a number
of peripherals in turn
A technique used to continuously check the data of a device
Why do programmed I/Os give devices priorities?
What does an interrupt I/O program do?
Allows the peripheral to signal its readiness by interrupting
the processor.
Why are interrupts put in place?
To handle synchronous events and improve system capacity
To improve the programmed I/O by not requiring
the program to sit idle while waiting for a peripheral to become
ready. (aka Efficiency)
True or false: When an interrupt I/O happens, it requires action from the CPU for each data to be transferred.
What happens when there is an interrupt?
An interrupt sequence happens, which is an event that causes the CPU to initiate a fixed
sequence
The current execution of a program is fast-forwarded and the control is transferred to a specific interrupt handler.
What happens when an interrupt is ready to transfer data?
It sets its ready flag in the
status register and asserts a control line (IREQ) connected to the
CPU.
The interrupt controller signals the CPU to stop its future operations and prioritize the interrupt.
True or false: During an interrupt sequence, as soon as it is able (often at the end of the current instruction)
the CPU then stops what it is doing, stores enough information to resume later and starts executing an interrupt routine.
What does the CPU do after executing an interrupt routine?
Resumes the interrupted program or task without any other information
Prioritizes everything completely
Uses the
information stored at the beginning of the interrupt to return the CPU
to executing the interrupted program.
What is an Interrupt Vector Table (IVT)?
A table with an index that contains an address for every peripheral device.
True or false: Many devices are able to interrupt.
True or false: There is a list of addresses for
the interrupt routines and one is chosen by using the interrupt
identifier as an index into the Interrupt Vector Table.
True or false: Whenever a peripheral is ready to transfer data it is necessary to
service its within a reasonable amount of time or else subsequent data
may be lost.
True
False
True or false: Faster peripherals require faster servicing
What happens if two or more peripherals are ready at the same time?
The faster one is serviced first
since the slow one can wait a little while.
The system will always prioritize the peripherals based on the order in which they were ready.
How can multiple interrupt requests be resolved?
By using a
priority interrupt scheme where a hardware priority
encoder assigns every device a priority and sends the lowest priority device to the
CPU.
By using a
priority interrupt scheme where a hardware priority
encoder assigns every device a priority and sends the highest priority device to the
CPU.
How is a prioritized interrupt request formed?
By performing a logical OR of the peripheral's IREQ lines.
True or False: Interrupt requests are assumed to remain asserted until reset by
instructions in the service routine.
Interrupt requests are assumed to remain asserted until reset by
instructions in the service routine. Is this the most efficient technique?
Until a request is de-asserted it is not possible for another request to
be seen. What does this result in?
Blocking the peripherals
Data from a fast peripheral will be lost
while service routine is clearing a low priority
interrupt.
The system ignores the new requests
Until a request is de-asserted it is not possible for another request to
be seen. What would be a better system?
The request could be cleared quickly after the
request is noticed.
Use a request queue with the new requests at the very top.
Delay the new requests
Ignore the new requests until the first request is completed
What is Interrupt Acknowledgement?
Where computers have a signal generated by the CPU that is returned to
the peripheral as soon as the interrupt is detected.
What does Interrupt Acknowledgement do?
Clear the interrupt request from that device and allows other
devices to use the interrupt line.
Ignore the interrupting device and continuing with the current request
This clears the interrupt request from that device and allows other
devices to use the interrupt line.
True or False: By using an interrupt acknowledgement, it's possible to construct a simpler
priority scheme.
What happens during priority interrupts ?
The interrupt request is ignored by all systems
The CPU is able to determine priority by which device the acknowledgement is sent to.
The interrupt request is passed from one device to the next until it reaches the Memory.
What is a daisy chain in priority interrupts?
Where all the interrupt request lines are OR’ed together like a daisy chain crown.
A type of chain used in data storage named after daisy chain crowns.
True or false: The CPU IACK is connected directly to the highest priority device, so if more than one request has been made the highest priority device
sees it first.
The CPU IACK is connected directly to the highest priority device. What happens because of this in a priority daisy chain?
If the highest priority device has the CPU but doesn't have a request, what does it do?
It passes the IACK along to the
next device, and so on
to the lowest priority device, which will receive an
acknowledgement only if no other device has made a request.
It ignores the requests and moves on to the lowest-priority device
True or false: In order to ensure a fast response to a high priority interrupt, it is possible
to allow interrupts to interrupt interrupts.
What is a nested interrupt?
An interrupt that specifically interrupts certain requests
It allows a higher priority device to be serviced
quickly even if a lower priority device is being serviced.
