WorksheetsComputer Architecture Quiz
Total questions: 53
Worksheet time: 32mins
The operation of the processor is defined in terms of _____ it exectutes referred to as ____.
a. machine instructions
b. operations
c. computer instructions
d. clock cycles
A fast interrupt can be interrupted by normal interrupt. True or False?
True
False
List data processing instructions:
Arithmetic, mathematic
Logical, Arithmetic
Mathematic, Processing
The collection of different instructions that the _ can execute is referred to as the _:
processor
processor's instruction set
Show a formula for calculation of total time required for a pipeline with k stages to execute n instructions and with cycle time tau
What is the type of addressing mode given by the algorithm EA = (A)?
(a)
Why do we need a pointer in a stack?
We need it to store the address of the top of the stack
We need it to store the address of the back of the stack
We need it to store the address of the top of the block
We need it to store the address of the back of the block
This set of registers contain status information
(a)
In the ARM architecture, the PC is stored in this register
(a)
Inputs for the operation are called
Source operand reference
Opcode
Processing system
(R1) = 10100101 and (R2) = 11111111. What is the result of (R1) XOR (R2) = ?
(a)
Consider an expression X = X + Y.X and Y correspond to locations 400 and 401 in a main memory. Show the steps to accomplish this calculations with machine instructions
Operation is determined by a binary code, known as
opcode
Operation code
IBBE
The first stage in the interrupt cycle execution:
In the first step, the contents of the PC are transferred to the MBR, so that they can be saved for return from the interrupt
: In the first step, the contents of the PC are transferred to the MBR, so that they go to the stack
Categories of user-visible registers are
General purpose, Data, address, condition codes
address, condition codes
Address ,General purpose, Data,
Condition codes
A conditional branch instruction makes the address of the next instruction to be fetched unknown. True of False?
True
False
The name of the CPSR register stands for
current status program register
Before status program register
STRB R0, [R1, #12]!. What type of indexing is used in the given instruction?
(a)
In the ARM architecture, the PC register is visible for all modes of execution. True or False?
True
False
In a system without virtual memory, the EA will be either a main memory address or a register. True of False?
True
False
List elements of machine instruction
Operation
Operation code, Source operand reference, result operand reference, next instruction reference
Result operand reference,Operation code, Source operand reference,
Result operand reference, Next instruction reference
For a given instruction length, there's clearly a trade-off between the number of opcodes and the power of addressing mode. True or False?
True
False
No memory reference to obtain the operand. This is advantage of the addressing mode called _
Immediate addressing
Indirect addressing
Direct addressing
Opcodes are represented by abbreviations called ___
a. instruction
b. mnemonics
c. immediates
d. operands
Displacement addressing combines the capabilities of which type addressing modes?
a. Direct and immediate
b. Direct and stack
c. Direct and register
d. Direct and register indirect
Thumb instructions are unconditional, so the condition code field is not used. True or False?
a. True
b. False
A size of instructions in the Thumb instruction set?
a. 32 bits
b. 16 bits
c. 64 bits
d. 8 bits
List the types of hazards
a. Resource, Data
b. Resource, Data, Control, Transfer
c. Resource, Data, Control
d. Resource, Control
What addressing mode is used for indexing?
a. Direct and register
b. Stack
c. Displacement
d. Immediate
The register indirect addressing requires two memory references. True or False?
a. True
b. False
This register contains the address of a location in memory
a. MBR
b. MAR
c. PC
d. IR
This register contains the address of an instruction to be fetched
a. PC
b. MBR
c. MAR
d. IR
What does the fetch stage perform?
Reads the next instruction from memory into the processor
Reads the current instruction from memory into the processor
Reads the next instruction from memory into the another part of the memory
Reads the next instruction from processor into the memory
List data processing instructions
a. test and branch instructions
b. logic instructions, test and branch instructions
c. arithmetic, I/O instructions
d. arithmetic, logic instructions
What is the type of addressing mode given by the algorithm Operand = A?
a. Operand
b. Register indirect
c. Direct
d. Immediate
How many execution modes does the ARM architecture support?
a. 8
b. 6
c. sometimes 6, sometimes 7
d. 7
No memory reference to obtain the operand. This is advantage of the addressing mode called ___
a. Immediate direct
b. Register
c. Immediate
d. Direct
Data registers can be employed in the calculation of an operand address. True or False?
a. False
b. True
(R1) = 10100101 and (R2) = 00001111. What is the result of (R1) AND (R2) = ?
a. 00010101
b. 00000101
c. 00011011
d. 10100101
What does the fetch stage perform?
a. Reads the next instruction from memory into the processor
b. Reads the current instruction from memory into the processor
Status information is contained in this set of registers:
a. MAR
b. MBR
c. PSW
d. PC
What is the type of addressing mode given by the algorithm EA = A?
a. Register indirect
b. Register
c. Indirect
d. Direct
In a virtual memory system, the EA is a virtual address or a register. True or False?
a. False
b. True
In this type of shift operation, the data are treated as a signed integer and the sign bit is not shifted.
a. Logical shift left
b. Logical
c. Arithmetic
d. Arithmetic shift right
What is the type of addressing mode given by the algorithm EA = (R)?
a. Direct
b. Register indirect
c. Register direct
d. Indirect
In a system without virtual memory, the EA will be either a main memory address or a register. True or False?
a. False
b. True
The memory address is the base register value. An offset is added or subtracted from the base register value and the result is written back to the base register. What type of indexing is this?
a. Offset
b. Postindex
c. No such indexing exists
d. Preindex
What is the type of addressing mode given by the algorithm EA = A + (R)?
a. Register indirect
b. Displacement
c. Indirect
d. Register-displacement
These instructions operate on the bits of a word as bits rather than as numbers
a. Logic
b. I/O
c. Branch
d. Arithmetic
List main components of a CPU?
a. ALU, system bus, control unit
b. ALU, registers, internal CPU bus
c. ALU, registers, control unit
d. ALU, control unit, control paths
In the ARM architecture, the stack pointer address is stored in this register
a. R15
b. R13
c. R18
d. R14
This register contains a word of data to be written to memory or the word most recently read.
a. MAR
b. IR
c. MBR
d. PC
List the stages of instruction cycle
a. Fetch, Execute, Interrupt
b. Fetch, Encode, Execute, Decode, Interrupt
c. Fetch, Encode, Execute, Interrupt
d. Fetch, Decode, Interrupt
