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WorksheetsVerilog TCL Quiz
Total questions: 21
Worksheet time: 11mins
What is the default value for reg data type
0
1
x
d
In continuous assignment left hand side must be
Net
Reg
Scalar or Vector Net
Scalar or Vector Net
If x=4 b1100 then x<<2 is
4 b1000
4 b0000
4 b0011
4 b0110
#40 $finish indicates
end of simulation time
end of simulation after 40 time units
suspend simulation at 40 time units
delay for 40 time units and then execute next line after $finish
What do you mean by logic synthesis?
RTL description is converted in terms of logic gates by the use of synthesis tool
RTL description is simulated and the simulation waveforms are shown by synthesis tools
RTL description is remodelled from behavioural to data flow modelling by synthesis tools
RTL description is checked for any errors by synthesis tools
what is the correct set of Verilog code to swap contents of two register with and without temporary registers.
What is wrong with following piece of code
Nothing wrong
incorrect a and b can overflow as it is incremented in an infinite loop
Simulation may not advance since forever doesn't have any timing control
A forever block cannot be used inside an initial block
What is order of execution for below code?
Zero delay control statement is executed first
Zero delay is executed only after all other statements
are executed in that simulation time and order of zero
delay statement is non deterministic
Zero delay control statement is executed last
Which is true about task and function
Task and function contain always and initial blocks
Task and function do not contain always and initial blocks
Task and function do not contain behavioral statement
Task and function can not have global variables called
For the below code segment given below
Values of a and b are swapped
Values of a and b cannot be swapped
Values of a and b can be swapped depending on simulato
Can t determine
Give a Verilog statement that instantiates the below RTL_circuit, with the instance name RT1, so that x has a delay of 7 time units and y has a delay of 5 time units
RTL_circuit #(7,5) RT1(y,x,a,b,c,d);
RTL_circuit #(5,7) RT1(x,y,a,b,c,d);
#(5,7) RTL_circuit RT1(y,x,a,b,c,d);
RTL_circuit #(7,5) RT1(x,y,a,b,c,d);
what is the output of the below code snippet
0
1
Error
X
What is the value of signal "out" at the end of simulation
1
0
X
undeterministic
Which of the following statements is true
Both task and function can return value
Blocking assignments are allowed in both task and functions
Delay, clock, always and initial blocks, @ can be used inside both tasks and function definitions
Both task and functions can be called inside definition of a function
What are the values of signals a and b at the end of 2 clock cycles
a=1, b=0
a=0, b=1
a=0, b=0
a=1, b=1
Consider the following code followed by testbench, fill the missing dashes in testbench with appropriate option
wire a,b,cin;
reg sum, cout;
Either A or B can be used
reg a,b,cin;
wire sum, cout;
None of these
What is the output printed with the below code snippet
3
2
32
[expr $a%$b]
Which of the following code snippet is correct when you want to read the file “data.txt” line by line and save each line as a list element.
set fh [open data.txt w]
set text [read $fh]
set data [split $text "\n"]
set fh [open data.txt w+]
set text [read $fh]
set data [split $text "\n"]
set fh [open data.txt w+]
set text [read $fh]
set data [append $text "\n"]
set fh [open data.txt r]
set text [read $fh]
set data [append $text "\n"]
What is printed on terminal from the below snippet of TCL code
the data is found
Data not found
Syntax Error
No syntax error but does not print anything
Which of the following is the correct way to use the “if” statement in Tcl to test whether a variable called “my_var” is equal to 10?
if my_var = 10 { … }
if {my_var = 10} { … }
if (my_var == 10) { … }
if [my_var == 10] { … }
Which of the following is the correct way in Tcl to calculate the sum of two variables called “my_var1” and “my_var2” ans store output in variable called "sum"?
set sum [expr my_var1 + my_var2]
set sum = my_var1 + my_var2
set sum expr my_var1 + my_var2
set sum expr {my_var1 + my_var2}
