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Worksheets3 chương đầu KTMT
Total questions: 69
Worksheet time: 35mins
Name
Class
Date
1.
Câu 75.v1 Computer organization is the science that studies...
a)
a. computer structures and their using methodologies.
b)
b. computer components and their working methodologies.
c)
C. computer structures and their working methodologies.
d)
d. computer components and their running methodologies.
2.
Câu 93.v1 Computer architecture is the science and art of selecting and interconnecting hardware components to create computer that meet … goals
a)
a. functionality, efficiency and cost
b)
b. functionality, performance and cost
c)
c. functionality, performance and expensive
d)
d. functions, performance and cost
3.
Câu 41.v1 Which is NOT a correct statement about CPU instructions?
a)
a. Instructions are saved from CPU to memory after execution.
b)
b. Instructions are fetched from memory to CPU for execution.
c)
c.Instructions are stored in memory.
d)
d. One instruction has it own function.
4.
Câu 21.v1 System Design which includes all of the other hardware components within a computing system, such as…
a)
a.System connects and CPU off-load mechanisms.
b)
b.System connects and CPU on-load mechanisms.
c)
c.System interconnects and CPU on-load mechanisms.
d)
d.System interconnects and CPU off-load mechanisms.
5.
Câu 45.v1 What is NOT a component of the instruction set architecture?
a)
a. Memory addressing modes
b)
b. Address format
c)
c. Processor registers
d)
d. The instruction set
6.
Câu 64.v1 What is NOT a component of the instruction set architecture?
a)
a. Processor registers
b)
b. The instruction set
c)
c. Address and data formats
d)
d. Memory addressing
7.
Câu 65.v1 System buses are sets of wires to connect CPU with other components of a computer. System buses consist of...
a)
a. A bus, B bus and C bus.
b)
b. A bus, C bus and D bus.
c)
c. B bus, C bus and D bus.
d)
d. B bus, D bus and C bus.
8.
Câu 73.v1 What is the computer component that fetches instructions from memory, decodes and executes instructions ?
a)
a. ALU
b)
b. CU
c)
c. Registers
d)
d. CPU
9.
Câu 118.v1 Three components of computer architecture are…
a)
a.Instruction set architecture, Microarchitecture, Analysis and Design.
b)
b.Instruction set architecture, Microarchitecture, System Design.
c)
c.Instruction set architecture, Macroarchitecture, System Design.
d)
d.Instruction architecture, Microarchitecture, System Design.
10.
Câu 122.v1 What are correct 3 major components of a basic CPU?
a)
a.CU, ALU, Cache
b)
b.CU, ALU, Registers
c)
c.CU, Cache, Registers
d)
d.GPU, ALU, Registers
11.
Câu 130.v1 In computer functional block diagram, there are CPU, system bus,…
a)
a.external memory and peripheral devices.
b)
b.internal memory and peripheral devices.
c)
c.internal memory and output devices.
d)
d.external memory and input devices.
12.
Câu 134.v1 Internal memory is used to store instructions and data for CPU to process. Internal memory consists of …
a)
a.ROM and SAM
b)
b.RON and RAM
c)
c.ROM and RAM
d)
d.RON and SAM
13.
Câu 143.v1/v8 What is an output device?
a)
a.Scanner
b)
b.Keyboard
c)
c.Mouse
d)
d.Disk drive
14.
Câu 154.v1 Computer organization is a part of computer architecture and also called …
a)
a. instruction set architecture
b)
b. analysis and design
c)
c. system design
d)
d. microarchitecture
15.
Câu 171.v1 In computer systems, ... numbering system is used to represent data.
a)
a. Decimal
b)
b. Hexadecimal
c)
c. Binary
d)
d. Octal
16.
Câu 42.v2 Internal Bus is the communication channel of all CPU components. It supports ... ways of communication.
a)
a. three
b)
b. two
c)
c. four
d)
d. one
17.
Câu 56.v2 After CPU executes one instruction, the ... is loaded into PC register.
a)
a. next instruction
b)
b. memory address of next instruction
c)
c. next instruction of memory address
d)
d. memory address
18.
Câu 13.v2 What are the status flags of the FR register?
a)
a.CF, DF, AF, ZF
b)
b.TF, OF, AF, ZF
c)
c.CF, OF, AF, ZF
d)
d.CF, OF, AF, IF
19.
Câu 12.v2 The Control Unit (CU) decodes the instruction and generates ... for other units, such as ALU to execute the instruction.
a)
a.execution signal
b)
b.pulse
c)
c.command
d)
d.request
20.
Câu 22.v2 SP or Stack Pointer is the register that always points to ... of the stack.
a)
a.next frame
b)
b.the middle
c)
c.the bottom
d)
d.the top
21.
Câu 52.v2 Each bit of FR register stores the ... of the operation executed by ALU.
a)
a. result
b)
b. status of the result
c)
c. status
d)
d. state of the result
22.
Câu 68.v2 What are the CPU registers?
a)
a. PC, RC, MCR, A, Y, Z
b)
b. PK, IR, MRR, A, Y, Z
c)
c. PC, IR, MBR, A, Y, Z
d)
d. PC, IR, MBR, A, B, C
23.
Câu 76.v2 What are the common sizes of CPU registers?
a)
a. 4, 8, 16, 32
b)
b. 8, 16, 32, 64
c)
c.16, 32, 64, 128
d)
d. 32, 64, 128, 256
24.
Câu 85.v2 Accumulator(A) register is also used in data exchange with … devices.
a)
a. internal
b)
b. computer
c)
c. external
d)
d. input and output
25.
Câu 88.v2 What are characteristics of CPU registers?
a)
a. Very fast, small in number or size
b)
b. Very fast, small in number and size
c)
c. Very fast, small in counter and size
d)
d. Very fast, small in size and low frequency
26.
Câu 91.v2 What are 4 general purpose registers of the intel 8086 CPU?
a)
a. A, B, C, D
b)
b. AX, BX, SI, DI
c)
c. AX, BX, CX, DX
d)
d. A, X, Y, Z
27.
Câu 112.v2 IR or Instruction register is used to store the ... instruction.
a)
a.next executed
b)
b.current executed
c)
c.executed
d)
d.next
28.
Câu 115.v2 What are the inputs to the control unit (CU)?
a)
a.CLK, IR, ALU
b)
b.CLK, PC, ALU flags
c)
c.CLK, IR, flags
d)
d.CLK, IR, ALU flags
29.
Câu 125.v2 What are common arithmetic instructions supported by ALU?
a)
a. ADD, SBB, DIV, MUR, SHR, ROL
b)
b. ADD, SUB, DIV, MUL, SHF, ROF
c)
c. ADD, SUB, DIV, MUL, SHR, ROL
d)
d. ADB, SUB, DIV, MUL, SHR, ROR
30.
Câu 137.v2 What are common logic instructions supported by ALU?
a)
a.NOT, NAND, OR, XOR
b)
b.NOT, AND, OR, XOR
c)
c.NOT, AND, NOR, XOR
d)
d.NOT, AND, OR, XORR
31.
Câu 146.v2 Control Unit (CU) gets instruction from … register, decodes and generates signals to control other components of the system.
a)
a.MBR
b)
b.PC
c)
c.MAR
d)
d.IP
32.
Câu 149.v2 Size of CPU Accumulator (A) register is equivalent to CPU…
a)
a. data word.
b)
b. data size.
c)
c. data word length.
d)
d. word length.
33.
Câu 152.v2 Control Unit (CU) uses clock to synchronize activities of functional units inside CPU and between .. components.
a)
a. CPU and external
b)
b. CPU and internal
c)
c. CPU and GPU
d)
d. internal and external
34.
Câu 156.v2 When a program code is loaded into internal memory, the address of the first instruction of the program is set onto … register.
a)
a. IR
b)
b. FR
c)
c. PC
d)
d. MAR
35.
Câu 172.v2 When a program is executed, the operating system loads the program code stored in ... memory into ... memory.
a)
a. Internal/external
b)
b. ROM/RAM
c)
c. Disk/RAM
d)
d.External/internal
36.
Câu 176.v What is types of flags?
a)
a. status flags, control flags
b)
b. status flags, control flags, data flags
c)
c. status flags, control flags, address flags
d)
d. status flags, control flags, condition flags
37.
Câu 181. "MAR gets memory address of next instruction from ... and forwards it to ..."
a)
a. PC, address bus
b)
b. IR, data bus
c)
c. PC, control bus
d)
d. IR, control bus
38.
Câu 189.v What is NOT correct about internal bus?
a)
a. large bandwidth
b)
b. communication channel of all bus components
c)
c. support full duplex
d)
d. faster than external buses
39.
Câu 190.v What is incorrect statement?
a)
a. MAR is the interface between the CPU and the address bus
b)
b. MBR is the interface between the CPU and the data bus
c)
c. MBR gets instruction from data bus and forwards it to IR
d)
d. MAR gets memory address of next instruction from IR and forwards it to address bus
40.
Câu 193.v What is correct? "IR gets instruction from ... and forwards it to ... decoding"
a)
a. ROM, RAM
b)
b. MAR, ALU
c)
c. MBR, CU
d)
d. PC, RAM
41.
Câu 196.v What is correct statement about MAR and MBR registers?
a)
a. MAR is slower than MBR.
b)
b. MAR and MBR are interfaces between the CPU and system bus.
c)
c. MAR is the input and MBR is the output of the CPU.
d)
d. MAR is faster than MBR.
42.
Câu 28.v3 What is the addressing mode of the instruction "LOAD R1, 1000", where R1 is a CPU register?
a)
a. Indirect
b)
b. Relative
c)
c. Direct
d)
d. Immediate
43.
Câu 14.v3 CPU instruction is a ... which implements a single pre-defined operation of a processor.
a)
a.binary code
b)
b.machine code
c)
c.binary word
d)
d.hexa word
44.
Câu 20.v3 What is the number of addresses of operands of the instruction "ADD R1, A", where R1 is a CPU register and A is a memory location?
a)
a. 2
b)
b.1
c)
c.2.5
d)
d.1.5
45.
Câu 26.v3 What is the addressing mode of the instruction "LOAD Ri, X(PC)", where Ri is a CPU register?
a)
a.Relative
b)
b.Indirect
c)
c.Indexed
d)
d.Direct
46.
Câu 34.v3 Common groups of CPU intructions include...
a)
a. data movement group, arithmetic group, conditional and branching group.
b)
b. data movement group, computational group, conditional and looping group.
c)
c. data processing group, computational group, conditional and branching group.
d)
d. data movement group, computational group, conditional and branching group.
47.
Câu 47*.v3 What is the meaning of the instruction "ADD A, B, C", where A, B, C are memory locations?
a)
a. M[A] ← M[A] + M[B] + M[C]
b)
b. M[B] ← M[A] + M[C]
c)
c. M[A] ← M[B] + M[C]
d)
d. M[C] ← M[A] + M[B]
48.
Câu 63.v3 Addressing modes are methods that ... are organized.
a)
a. instruction operands
b)
b. instruction parts
c)
c. instruction elements
d)
d. command operands
49.
Câu 66.v3 What is the addressing mode of the instruction "MOVE (R1), 1000", where R1 is a CPU
a)
a. Indirect
b)
b. Direct
c)
c. Indexed
d)
d. Relative
50.
Câu 67.v3 Common control and sequencing instructions include...
a)
a. JUMP, CALL, RETURN, BRANCH-IF-CONDITION
b)
b. JUMP, CALL, RET, BRANCH-CONDITION
c)
c. JMP, CALL, RET, BRANCH-IF-CONDITION
d)
d. JUMP, CALL, RETURN, BRANCH-IF
51.
Câu 80*.v3 What is the meaning of the instructions "LOAD 1000, (R1)", where R1 is a CPU register?
a)
a. M[1000] -> M[R1]
b)
b. 1000 -> R1
c)
c. M[1000] <- R1
d)
d. M[1000] <- M[R1]
52.
Câu 84.v3 Instruction execution cycle is the ... that CPU completes the execution of the instruction.
a)
a. period of time
b)
b. periodic time
c)
c. clock of time
d)
d. number of clocks
53.
Câu 97.v3 Generally, an instruction has two parts of opcode and…
a)
a. values of operands
b)
b. address of operands
c)
c. destinations of operands
d)
d. sources of operands
54.
Câu 98.(v3) 0 address of operands is used in instructions that perform … operations, such as push and pop.
a)
a. string
b)
b. tree
c)
c. stack
d)
d. queue
55.
Câu 100.v3 Instruction execution is divided into phases or stages. One instruction can be executed in 5 stages, including…
a)
a. IC, ID, EX, MEM, WR
b)
b. IF, IR, EX, MEM, WR
c)
c. IF, ID, EX, MEM, WB
d)
d. IS, ID, EX, MEM, WB
56.
Câu 102.v3 What is the addressing mode of the instruction "LOAD R1, (1000)", where R1 is a CPU register?
a)
a. Indirect
b)
b. Relative
c)
c. Direct
d)
d. Immediate
57.
Câu 110.v3 What is the meaning of the instruction "LOAD Ri, X(PC)", where Ri is a CPU register?
a)
a.Ri <- M[X+PC]
b)
b.Ri <- X + M[PC]
c)
c.Ri <- X+PC
d)
d.Ri -> M[X+PC]
58.
Câu 123.v3 What is the addressing mode of the instruction "LOAD R1, #1000", where R1 is a CPU register?
a)
a.Indirect
b)
b.Immediate
c)
c.Relative
d)
d.Direct
59.
Câu 138.v3 What are correct typical addressing modes?
a)
a.Immediate, Direct, Indexed, Memory
b)
b.Immediate, Direct, Indexed, Relative
c)
c.Immediate, Direct, Index, Relative
d)
d.Immediate, Direct, Index, Relate
60.
Câu 139.v3 Which is NOT a correct statement about instruction execution cycle and its components of traditional CPUs?
a)
a.An execution stage may consist of some machine cycles.
b)
b.An execution stage may consist of some execution phases.
c)
c.One machine cycle consists of some clock cycles.
d)
d.An instruction execution cycle consists of some instruction execution stages.
61.
Câu 145.v3 Input and output (I/O) instructions are used to transfer data between ... and …
a)
a.the CPU / external devices.
b)
b.the computer / peripheral devices.
c)
c.the CPU / peripheral devices.
d)
d.the computer / internal devices.
62.
Câu 150.v3 What is the meaning of the instruction "SUBSTRACT R1, R2, R3", where Ri is a CPU register?
a)
a. R1 <- R1 - R2 - R3
b)
b. R3 <- R1 - R2
c)
c. R2 <- R1 - R3
d)
d. R1 <- R2 - R3
63.
Câu 153.v3 What is the meaning of the instruction “ADD R3,R2,R1” where Ri is a CPU register?
a)
a. R2 <- R3 + R1
b)
b. R3 <- R2 + R1
c)
c. R1 <- R2 + R3
d)
d. R3 <- R3 + R2 + R1
64.
Câu 155.v3 In CPU pipeline, the instruction execution is divided into stages and.... is executed by...
a)
a. each stage / a CPU component.
b)
b. CPU components / stages.
c)
c. a CPU component / each stage.
d)
d. stages/CPU components.
65.
Câu 160.v3 Which is NOT a correct statement about CPU instructions?
a)
a. An execution stage may consist of some execution phases
b)
b. One machine cycle consists of some clock cycle
c)
c. An execution stage may consists of some machine cycles
d)
d. An instruction execution cycle consists of some instruction execution stages.
66.
Câu 169.v3 What is the addressing mode of the instruction "LOAD Ri, X(Rind)", where Ri is a CPU register?
a)
a. Relative
b)
b. Direct
c)
c. Indexed
d)
d. Indirect
67.
Câu 177.v What are NOT elements of an instruction execution cycle
a)
a. Memory read cycle, Memory write cycle, Peripheral read cycle, Interrupt acceptance cycle
b)
b. Instruction fetch cycle, Memory read cycle, Peripheral read cycle, Bus free cycle
c)
c. Instruction fetch cycle, Memory read cycle, Peripheral read cycle, Bus read cycle
d)
d. Memory read cycle, Memory write cycle, Peripheral read cycle, Bus free cycle
68.
Câu 180.v Common arithmetic instructions include ...
a)
a. ADD, SUB, MULTIPLY, DIVIDE
b)
b. ADD, SUBTRACT, MULTIPLY, DIVIDE
c)
c. ADC, SUBTRACT, MULTIPLY, DIVIDE
d)
d. ADD, SUB, MUL, DIV
69.
Câu 186.v What is the addressing mode of the instruction "LOAD R1, (R2)", where Ri is a CPU register
a)
a. Direct
b)
b. Indirect
c)
c. Immediate
d)
d. Relative
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