WorksheetsLPC1768 Embedded Protocols UART, SPI and I2C
Total questions: 56
Worksheet time: 28mins
In LPC1768, the LCR (Line Control Register) is used to configure which of the following UART settings?
Baud rate
Data length, stop bits, and parity
Transmit and receive buffers
Interrupt priority
What does the RBR Register in LPC1768 store?
The UART baud rate
Data received from the UART
Data to be transmitted over UART
UART interrupt flags
In LPC1768 UART , the FDR Register is used for:
Calculating the UART baud rate more precisely
Configuring the number of stop bits
Managing UART interrupts
Enabling the UART peripheral
Which bit in the LSR indicates that the UART transmit holding register (THR) is empty in LPC1768?
Bit 0
Bit 1
Bit 5
Bit 7
What is the correct formula for calculating the baud rate in LPC1768's UART?
Baud Rate = PCLK / (DLL * 16)
Baud Rate = PCLK / (16 * (DLL + DLM))
Baud Rate = PCLK / (16 * (DLL + (DLM << 8)))
Baud Rate = PCLK / (DLL * FDR)
In LPC1768, which UART register is responsible for indicating that a framing error has occurred?
LSR
LCR
IER
RBR
If DLL = 0x01 and DLM = 0x00, what is the baud rate for UART in LPC1768 when PCLK = 1 MHz?
1 Mbps
9600 bps
115.2 kbps
62.5 kbps
In LPC1768 UART, the FCR Register is used to:
Control the FIFO buffer size
Enable or disable the FIFO buffers
Configure the baud rate
Set parity and stop bits
What is the correct sequence to initialize UART0 in LPC1768 C programming?
Configure PCONP, PINSEL0, LCR, DLM/DLL
Configure PCONP, PINSEL1, FCR, THR
Configure PINSEL0, PCONP, LCR, RBR
Configure DLM/DLL, THR, PCONP, RBR
In LPC1768 UART C programming, what does the following line configure for UART2?
UART2->LCR = (3 << 0) | (1 << 7);
8-bit data length and divisor latch access
7-bit data length and enable interrupts
8-bit data length and enable parity
8-bit data length and disable interrupts
In LPC1768 C programming, how do you check if data is available to read from UART2?
if (UART2->LSR & (1 << 5))
if (UART2->LSR & (1 << 0))
if (UART2->RBR)
if (UART2->LSR & (1 << 7))
Which register in LPC1768 is used to configure SPI in master mode?
SPCCR
SPCR
SPDR
SPSR
In LPC1768 SPI communication, what does the SPIF bit in the SPSR register indicate?
SPI is idle
SPI data transfer is complete
A fault occurred during transmission
SPI is configured as a slave
If PCLK = 1 MHz and SPCCR = 8, what is the resulting SPI clock frequency?
125 kHz
250 kHz
500 kHz
1 MHz
Which register in LPC1768 stores the data received from the slave during SPI communication?
SPRR
SPCR
SPDR
SPSR
What is the maximum clock rate for SPI communication if the PCLK = 1 MHz on LPC1768?
1 MHz
500 kHz
250 kHz
125KHz
Which mode in SPI communication ensures that data is sampled on the rising edge and shifted out on the falling edge?
Mode 0
Mode 1
Mode 2
Mode 3
How is SPI Mode 3 (CPOL = 1, CPHA = 1) configured in LPC1768 using the SPCR register?
SPCR |= (1 << 2) | (1 << 3);
SPCR &= ~(1 << 4);
SPCR |= (1 << 3) | (1 << 4);
SPCR |= (1 << 6);
In LPC1768, how is the SPI module configured as a master in C programming?
SPCR |= (1 << 3);
SPCR |= (1 << 2);
SPCR &= ~(1 << 3);
SPCR |= (1 << 5);
What is the main advantage of using interrupt-driven SPI communication in LPC1768 over polling-based communication?
It increases the clock speed.
It reduces CPU idle time and improves efficiency.
It simplifies the code.
It avoids hardware limitations.
How is a specific slave device selected in an SPI communication setup?
By setting the appropriate SCK line
By asserting the corresponding SS (Slave Select) line low
By changing the clock polarity
By sending a unique address to the slave
. In a single-master, multi-slave SPI configuration, what should the SSEL (Slave Select) pin status be on the master device?
Pulled high during communication
Asserted low only when communicating with the specific slave
Toggled for each data byte transfer
Pulled low continuously
. In a scenario where multiple SPI slaves are connected to a master, how do you prevent multiple slaves from responding at the same time?
By enabling only one SS pin at a time
By sending a start signal to only one slave
By sending different clock signals to each slave
By using a different MOSI pin for each slave
What is the behavior of the MISO line when the slave device is not selected (SS is high)?
It remains in a high-impedance state (Hi-Z)
It outputs zeroes
It echoes the master's clock signal
It continuously transmits data
. In SPI communication, what is the role of the clock polarity (CPOL) and clock phase (CPHA) settings?
They define how data is transmitted between multiple masters
They control the speed of the SPI clock
They configure the idle state of the clock and the data sampling points
They determine which slave will respond
What is the typical configuration for the SS (Slave Select) pin when using SPI in single-master, multi-slave mode?
Each slave has its dedicated SS pin connected to the master
All slaves share a single SS pin
SS is unused in multi-slave mode
The SS pin is toggled by the master for every byte transfer
What is the main function of the MAX7219/MAX7221 IC?
To control the brightness of LEDs
To drive 7-segment displays and LED matrices
To handle serial communication
To generate clock signals for SPI
When interfacing the MAX7219/MAX7221 with LPC1768, which SPI mode is required for proper synchronization /correct data transfer between the master and slave ?
SPI Mode 0 (CPOL = 0, CPHA = 0)
SPI Mode 1 (CPOL = 0, CPHA = 1)
SPI Mode 2 (CPOL = 1, CPHA = 0)
SPI Mode 3 (CPOL = 1, CPHA = 1)
What is the purpose of the DECODE MODE register in the MAX7219/MAX7221?
To set the brightness of the display
To define whether the data sent corresponds to a 7-segment or a raw LED pattern
To set the number of digits to display
To configure SPI clock speed
How many 7-segment display units can one MAX7219/MAX7221 drive simultaneously?
1
2
4
8
To display a number on the first digit of a 7-segment display connected to the MAX7219/MAX7221, which register should be addressed?
DIGIT0
DIGIT1
DIGIT2
SCAN LIMIT
What is the SCAN LIMIT register used for in the MAX7219/MAX7221?
To define the number of 7-segment digits to display
To set the SPI clock frequency
To reset the display
To enable brightness control
What happens if the DECODE MODE is set to 0xFF in MAX7219/MAX7221?
All digits will decode data as 7-segment data
All digits will display a test pattern
All digits will be turned off
All digits will decode raw LED data
What is the maximum current that can be driven by the MAX7219/MAX7221 per segment?
10 mA
20 mA
40 mA
60 mA
Which SPI clock frequency would be required for proper communication between the LPC1768 and MAX7219?
Higher than 10 MHz
Exactly 1 MHz
Less than 10 MHz
100 kHz
What does the I2C protocol use to communicate between master and slave devices?
2-wire synchronous multi-master, multi-slave full-duplex serial communication
2-wire synchronous multi-master, mult-slave half-duplex serial communication
2-wire synchronous single-master, multi-slave full-duplex serial communication
2-wire synchronous single-master, multi-slave half-duplex serial communication
What does the I2C protocol use to communicate between master and slave devices?
SCLK, MISO,MOSI,SS lines
TXD,RXD lines
SCL,SDA lines
Parallel lines
In the LPC1768 I2C module, which register is used to set the clock speed?
I2CONSET
I2SCLH & I2SCLL
I2DAT
I2CONCLR
Which type of data transfer is not supported by the I2C protocol?
Master to slave
Slave to master
Full-duplex transfer
Multi-master mode
What is the purpose of the clock stretching mechanism in I2C?
To generate a higher clock speed
To allow the slave to hold the clock line low until it is ready
To reset the I2C bus
To stop data transfer temporarily
What is the typical maximum data rate supported by the standard mode of I2C?
100 kHz
400 kHz
1 MHz
3.4 MHz
In I2C communication, how is arbitration handled when two masters initiate communication simultaneously?
The master with the higher address wins
The master with the lower address wins
The clock speed is increased
The bus is reset automatically
What does the I2C acknowledge (ACK) signal indicate?
Start of communication
Successful data reception
Error in data transmission
End of communication
In the LPC1768 I2C peripheral, what is the purpose of the I2CONSET register?
To read the received data
To control I2C operations like start, stop, and acknowledgment
To set the clock frequency
To configure interrupt settings
. In the LPC1768 I2C C programming, which bit must be set in I2CONCLR to clear the interrupt flag?
SI
STA
STO
AA
When configuring the I2C clock in LPC1768, which registers are modified to set the high and low times of the SCL signal?
I2SCLH and I2SCLL
I2CONSET and I2CONCLR
I2DAT and I2ADR
I2MASK and I2STAT
When using the LPC1768 I2C peripheral in master mode, what is the purpose of setting the STA bit in the I2CONSET register?
To stop the I2C communication
To start the I2C communication
To acknowledge the data transfer
To enable clock stretching
In LPC1768 I2C, clearing which bit in the I2CONCLR register will disable the Acknowledge (ACK) signal?
SI
STA
AA
STO
In LPC1768, What is the minimum and maximum i2c clock speed achievable if PCLK=1MHz
15.25Hz & 1MHz
3.92KHz & 512KHz
1 Hz & 256KHz
7.6 Hz & 128KHz
What is the format of a 7-bit I2C slave address field of I2C frame?
In two byte with the first byte as the address and the second byte as R/W
In two byte with the first byte as R/W and the second byte as address
In one byte with the first 7 bits as the address and the last bit as R/W
In one byte with the first bit as R/W and remaining 7 bits as the address
How is a 10-bit I2C address formatted and transmitted over the bus?
The first byte contains first 8 bits of the address while the second byte contains the remaining 3 bits of the address followed by the R/W bit
The first byte contains first 7 bits of the address and the R/W bit while the second byte contains the remaining 3 bits of the address
The first byte contains the fixed 1111 followed by the first 3 bits of the address and the R/W bit, while the second byte contains the remaining 8 bits of the address.
The first byte contains the the first 3 bits of the address , while the second byte contains the remaining 7 bits of the address and the R/W bit.
What is the 7-bit I2C address format for the 24C04 EEPROM when it is interfaced with an LPC1768 as an I2C master?
0x50 to 0x53 (based on A0 and A1 pins configuration)
0xA0 to 0xA7
0x00 to 0x03
0x40 to 0x47
In a random byte read operation from a 24C04 EEPROM, what sequence of operations must be followed?
Start → Send Slave Address (with R/W bit set to 0) → Send Memory Address → Restart → Send Slave Address (with R/W bit set to 1) → Read Data → Stop
Start → Send Slave Address (with R/W bit set to 1) → Read Data → Stop
Start → Send Memory Address → Read Data → Stop
Start → Send Slave Address (with R/W bit set to 1) → Write Data → Stop
In continuous read mode from the 24C04 EEPROM, what happens when the end of memory is reached?
The device halts the I2C bus until a stop condition is detected
The device wraps around to the beginning of memory
The device continues reading but returns the last valid byte
The device generates a NACK and stops communication
In a write operation to the 24C04 EEPROM, what is the required delay for the memory to complete the internal write cycle before it can accept another operation?
1 ms
5 ms
10 ms
50 µs
What should be done after writing a byte to the 24C04 EEPROM to ensure that the next write starts at a new memory location?
Send a restart condition
Send a stop condition and then a new start condition
Send an acknowledge signal
Send a NACK signal
