WorksheetsDSD QUIZZ 2 2023 Batch
Total questions: 10
Worksheet time: 5mins
Name
Class
Date
1.
Which model uses transistors as their basic components
a)
Switch level
b)
Gate Level
c)
Circuit Level
d)
Layout Level
2.
State true or false for the statement ‘Verilog is case sensitive’
a)
True
b)
False
3.
What is Verilog?
a)
A programming language for hardware description
b)
A high-level programming language for software development
c)
A data visualization tool
d)
An operating system
4.
Which one of the following represents a hardware component in Verilog
a)
Module
b)
Function
c)
Loop
d)
Variable
5.
What is the purpose of ‘assign’ statement in Verilog
a)
To initialize variables
b)
To specify input/output ports of a module
c)
To implement continuous assignments for combinational logic
d)
To define a new module
6.
In RTL Design, What is a ‘register’
a)
A clock signal generator
b)
A storage element for data
c)
An arithmetic logic unit (ALU)
d)
A type of programming language
7.
What is the default value of the reg data type
a)
0
b)
1
c)
Z
d)
X
8.
What is the purpose of the ‘posedge’ keyword in Verilog?
a)
To specify a positive edge-triggered flip flop
b)
To specify a negative edge-triggered flip flop
c)
To specify a synchronous reset
d)
To specify an asynchronous rese
9.
How are multi-bit signals represented in Verilog
a)
As an array of bits
b)
As separate single-bit signals
c)
As a string of characters
d)
As a floating-point number
10.
What is the purpose of the ‘case’ statement in Verilog
a)
To define a new module
b)
To specify simulation time
c)
To declare variables
d)
To implement conditional logic
100 %
