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WorksheetsUnit 3 Assessment
Total questions: 26
Worksheet time: 32mins
Discuss how the transparent D-latch differs from other flip-flops.
What happens to the output Q when J=0, K=0, and CLK is at the rising edge?
No Change
Clear
Set
Toggle
In a Positive Edge Triggered J/K flip-flop, when J=0, K=0, and CLK is at the rising edge, the output Q is (a) .
0
1
The flip-flop's CLOCK input is ______ sensitive, meaning the flip-flop's output changes on the ______ (rising or falling) of the CLOCK input.
(a)
How are flip-flops used in data synchronization?
A frequency divider produces a digital output signal that is (a) the frequency of the input.
Double
Half
Same
Quarter
Based on the waveform diagram, what is the relationship between Clock_In and Clock_Out?
A shift register is a group of flip-flops arranged so that the values stored in the flip-flops are shifted from one flip-flop to the next for every (a) .
Explain the timing diagram for a shift register as shown in the image. Discuss the role of each signal (D4, D3, D2, D1, Data_In, Clock) in the operation of the shift register.
What does SSI stand for in the context of Digital Logic?
(a)
Explain the ripple effect in asynchronous counters.
Which of the following best describes an asynchronous counter?
A counter that operates in sync with a clock signal
A counter that operates independently of a clock signal
A counter that uses synchronous flip-flops
A counter that uses asynchronous flip-flops.
Calculate the number of states for a system with 3 flip-flops.
(a)
Explain the function of the reset circuit in the Modulus Asynchronous Counter.
What type of counter is the 74LS93 IC?
8-bit ripple counter
4-bit ripple counter
2-bit ripple counter
16-bit ripple counter
The divide-by-two and divide-by-eight sections can be cascaded to create a divide-by-sixteen circuit when a wire is added between which two points?
From (a) to (b)
What type of counter is shown in the design example circuit diagram?
4-Bit Synchronous, Modulus-13 Counter
4-Bit Asynchronous, Modulus-13 Counter
8-Bit Asynchronous, Modulus-13 Counter
4-Bit Asynchronous, Modulus-10 Counter
What is a trade-off for the convenience of an all-in-one package in most MSI integrated circuits?
Increased flexibility
Lack of design flexibility
Higher cost
Smaller size
Fill in the blank: The primary limitations of the 74LS93 are that the flip-flops are not pre-settable, thus the count must always start at (a) .
What happens to the output count on every rising edge of the clock in the 74LS163 timing diagram?
It is decremented by one.
It remains the same.
It is incremented by one.
It is reset to zero.
Fill in the blank: The ~BO signal in the 74LS193 is for (a) .
The ~CO signal in the 74LS193 is used for (a) .
The LOAD input is set to a logic (0) in the 74LS193 counter. What is the immediate effect?
Outputs are cleared
Outputs are loaded with input data
Counter stops
Counter resets
Setup Time (tₛ) is the time interval ______ the active transition of the clock signal.
before
after
during
none of the above
What is the function of the EN input in a Transparent D-Latch?
The 74LS74 has which of the following features?
A) Preset
B) Clear
C) Complementary Outputs
D) All of the above.
