Computer _________ refers to those attributes that have a direct impact on the logical execution of a program.

Architectural attributes include __________ .

_________ attributes include hardware details transparent to the programmer.

It is a(n) _________ design issue whether a computer will have a multiply instruction.

It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system.

A __________ system is a set of interrelated subsystems.

An I/O device is referred to as a __________.

When data are moved over longer distances, to or from a remote device, the process is known as __________.

The _________ stores data.

The __________ moves data between the computer and its external environment.

A common example of system interconnection is by means of a __________.

A _________ is a mechanism that provides for communication among CPU, main memory, and I/O.

_________ provide storage internal to the CPU.

The __________ performs the computer's data processing functions.

The _________ was the world's first general-purpose electronic digital computer.

The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________.

The ENIAC used __________.

The ENIAC is an example of a _________ generation computer.

The __________ interprets the instructions in memory and causes them to be executed.

The memory of the IAS consists of 1000 storage locations called __________.

The __________ contains the 8-bit opcode instruction being executed.

During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR.

Second generation computers used __________.

The __________ defines the third generation of computers.

The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate.

With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel.

The __________ measures the ability of a computer to complete a single task.

ARM processors are designed to meet the needs of _________.

One increment, or pulse, of the system clock is referred to as a _________.

At a top level, a computer consists of CPU, memory, and I/O components.

The basic function of a computer is to execute programs.

Program execution consists of repeating the process of instruction fetch and instruction execution.

Interrupts do not improve processing efficiency.

An I/O module cannot exchange data directly with the processor.

A key characteristic of a bus is that it is not a shared transmission medium.

Interrupts do not improve processing efficiency.

An I/O module cannot exchange data directly with the processor.

A key characteristic of a bus is that it is not a shared transmission medium.

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.

In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay.

It is not possible to connect I/O controllers directly onto the system bus.

The method of using the same lines for multiple purposes is known as time multiplexing.

Timing refers to the way in which events are coordinated on the bus.

With asynchronous timing the occurrence of events on the bus is determined by a clock.

Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance.

The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit.

A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet.

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton.

The von Neumann architecture is based on which concept?

A sequence of codes or instructions is called __________.

The processing required for a single instruction is called a(n) __________ cycle.

A(n) _________ is generated by a failure such as power failure or memory parity error.

A(n) _________ is generated by some condition that occurs as a result of an instruction execution.

The interconnection structure must support which transfer?

A bus that connects major computer components (processor, memory, I/O) is called a __________.

The __________ are used to designate the source or destination of the data on the data bus.

The data lines provide a path for moving data among system modules and are collectively called the _________.

A __________ is the high-level set of rules for exchanging packets of data between devices.

Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time.

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer.

The TL supports which of the following address spaces?

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects.

No single technology is optimal in satisfying the memory requirements for a computer system.

A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external.

External memory is often equated with main memory.

The processor requires its own local memory.

Cache is not a form of internal memory.

The unit of transfer must equal a word or an addressable unit.

Both sequential access and direct access involve a shared read-write mechanism.

In a volatile memory, information decays naturally or is lost when electrical power is switched off.

To achieve greatest performance the memory must be able to keep up with the processor.

Secondary memory is used to store program and data files and is usually visible to the programmer only in terms of individual bytes or words.

The L1 cache is slower than the L3 cache.

With write back updates are made only in the cache.

It has become possible to have a cache on the same chip as the processor.

All of the Pentium processors include two on-chip L1 caches, one for data and one for instructions.

Cache design for HPC is the same as that for other hardware platforms and applications.

__________ refers to whether memory is internal or external to the computer.

Internal memory capacity is typically expressed in terms of _________.

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.

"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________.

individual blocks or records have a unique address based on physical location with __________.

For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.

The ________ consists of the access time plus any additional time required before a second access can commence.

A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.

A line includes a _________ that identifies which particular block is currently being stored.

__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.

When using the __________ technique all write operations made to main memory are made to the cache as well.

The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit.

The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers.

In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory.

A logical cache stores data using __________.