wayground logo

Free Printable Worksheets

Font size

S
M
L
XL
Worksheets

Computer Architecture Quiz

Total questions: 89

Worksheet time: 45mins

Name
Class
Date
1.

The Small extremely fast, RAM's are call as_____?

a)

Cache

b)

Stack

c)

Heaps

d)

Registers

2.

Which of the architecture saves memory?

a)

Harvard

b)

Von Neumann

c)

Harvard & Von Neumann

d)

None of them

3.

During the execution of the instructions, a copy of the instructions is placed in the _____

a)

HDD

b)

RAM

c)

Cache

d)

Register

4.

Which of these is a valid byte?

a)

11011011

b)

10022011

c)

AA-AA-BB-BB

d)

00-11-FF-F

5.

The ALU makes use of _______ to store the intermediate results.

a)

Accumulators

b)

Registers

c)

Heap

d)

Stack

6.

A source program is usually in _______

a)

Assembly language

b)

Machine level language

c)

High-level language

d)

Natural language

7.

How many possible values can we have with 8 bits?

a)

8

b)

1 byte

c)

256

d)

127

8.

The binary valua of the ASCII letter "c" is 01100011. Its decimal value is _____

a)

123

b)

100

c)

45

d)

99

9.

Where does the CPU store its computations?

a)

Registers

b)

External Data Bus

c)

Binary

d)

Processor

10.

Which memory device is genrally made of semiconductors?

a)

Floppy disk

b)

CDROM

c)

DVD

d)

RAM

11.

_____ are numbers and encoded characters, generally used as operands.

a)

Information

b)

Stored values

c)

Output

d)

Data

12.

The input devices can send information to the processor when _____

a)

When the SIN status flag is set

b)

When the data arrives regardless of the SIN flag

c)

All of them

d)

None of them

13.

The ______ format is usually used to store data

a)

All of them

b)

Decimal

c)

Hexadecimal

d)

Octal

14.

The 8-bit encoding format used to store data in a computer is ______

a)

ASCII

b)

EBCDIC

c)

ANCI

d)

UNICODE

15.

The control unit controls other units by generating ___________

a)

Control signals

b)

Timing signals

c)

Transfer signals

d)

Command Signals

16.

To reduce the memory access time we generally make use of ______

a)

Heaps

b)

Higher capacity RAM's

c)

SDRAM's

d)

Cache's

17.

The time delay between two successive initiations of memory operation _______

a)

Memory access time

b)

Memory search time

c)

Memory cycle time

d)

Instruction delay

18.

Which of the register/s of the processor is/are connected to Memory Bus?

a)

PC

b)

MAR

c)

IR

d)

Both PC and MAR

19.

ISP stands for _________

a)

Instruction Set Processor

b)

Information Standard Processing

c)

Interchange Standard Protocol

d)

Interrupt Service Procedure

20.

____ is used to choose between incrementing the PC or performing ALU operations.

a)

Conditional codes

b)

Multiplexer

c)

Control unit

d)

None of them

21.

The registers, ALU and the interconnection between them are collectively called as _____

a)

process route

b)

information trail

c)

information path

d)

data

22.

The first computer constructed using vaccum tubes was _____

a)

EDVAC

b)

ENIAC

c)

EDIAC

d)

IBM PC

23.

_____ is not one of the four basic functions of a computer

a)

Data processing

b)

Data storage

c)

Data movement

d)

I/O processing

24.

The second generation of computers based on _____

a)

Vacuum tubes

b)

Transistors

c)

IC

d)

VLSI

25.

The third generation of computers based on _____

a)

Vacuum tubes

b)

Transistors

c)

IC

d)

VLSI

26.

The binary representation of -7 is _____ o

a)

0111

b)

1001

c)

1101

d)

1011

27.

What is the function of MAR?

a)

Read a word from memory

b)

Specify an address of memory

c)

Contains the 8 bit opcode o

d)

Store address of the next instruction

28.

What is the function of MBR?

a)

Read a word from memory

b)

Specify an address of memory

c)

Contains the 8 bit opcode

d)

Store address of the next instruction

29.

Which registers can interact with the secondary storage?

a)

PC

b)

IR

c)

R1

d)

MAR

30.

The binary representation of -15 is _____

a)

00100000

b)

01000000

c)

10000000

d)

11110001

31.

_____ is the binary representation of -1:

a)

00000000

b)

00001111

c)

11110000

d)

11111111

32.

The registers and ALU are connected by using _____

a)

Control path

b)

Process route

c)

Information path

d)

Data path

33.

If a processor clock is rated as 3 GHz then its clock period is _____

a)

3.00*10^-10 sec

b)

3.00*10^-9 sec

c)

0.33*10^-10 sec

d)

0.33*10^-9 sec

34.

If a processor clock is rated as 1.8 GHz then its clock period is _____

a)

5.55*10^-10 sec

b)

5.55*10^-9 sec

c)

0.55*10^-10 sec

d)

55.5*10^-9 sec

35.

The main virtue for using single Bus structure is ____________

a)

Fast data transfers

b)

Cost effective connectivity and speed

c)

Cost effective connectivity and ease of attaching peripheral devices

d)

None of them

36.

ANSI stands for __________

a)

American National Standards Institute

b)

American National Standard Interface

c)

American Network Standard Interfacing

d)

American Network Security Interrupt

37.

In multiple Bus organisation, the registers are collectively placed and referred as ______

a)

Set registers

b)

Register file

c)

Register Block

d)

Map registers

38.

The ISA standard Buses are used to connect ___________

a)

RAM and processor

b)

GPU and processor

c)

Harddisk and Processor

d)

CD/DVD drives and Processor

39.

Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?

a)

A

b)

B

c)

A and B take the same time

d)

Insufficient information

40.

For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?

a)

ISA

b)

ANSA

c)

Super-scalar

d)

All of them

41.

An optimizing Compiler does _________

a)

Better compilation of the given piece of code

b)

Takes advantage of the type of processor and reduces its process time

c)

Does better memory management

d)

None of them

42.

When Performing a looping operation, the instruction gets stored in the ______

a)

Registers

b)

Cache

c)

System Heap

d)

System stack

43.

The average number of steps taken to execute the set of instructions can be made to be less than one by following _______

a)

ISA

b)

Pipe-lining

c)

Super-scaling

d)

Sequential

44.

Which method/s of representation of numbers occupies a large amount of memory than others?

a)

Sign-magnitude

b)

1's complement

c)

2's complement

d)

1's & 2's compliment

45.

What is the maximum addressable memory of a 32-bit microprocessor with 24-bit address?

a)

16 MB

b)

16 Mbits

c)

16 GB

d)

16 Gbits

46.

A complete microcomputer system consist of _____

a)

Microprocessor

b)

Memory

c)

Peripheral equipment

d)

All of them

47.

CPU fetches the instruction pointed by____

a)

MR

b)

MAR

c)

MBR

d)

PC

48.

The processing required for a single instruction is called an _____

a)

Instruction processing

b)

Instruction cycle

c)

Memory instruction

d)

Memory cycle

49.

The fetched instruction is loaded into a register in the processor known as the _____

a)

Memory

b)

Kernel

c)

Instruction register

d)

SSD

50.

The processor may perform some arithmetic or logic operation on data is _____

a)

Data processing

b)

Control

c)

Processor

d)

Data transferring

51.

SDRAM stands for _____

a)

Static dynamic random access memory

b)

System dynamic random access memory

c)

Synchronous dy

52.

s _____

a)

Data processing

b)

Control

c)

Processor

d)

Data transferring

53.

SDRAM stands for _____

a)

Static dynamic random access memory

b)

System dynamic random access memory

c)

Synchronous dynamic random access memory

d)

Syndrome dynamic random access memory

54.

A processor performing fetch or decoding of different instruction during the execution of another instruction is called _____

a)

Parallel Computation

b)

Pipe-lining

c)

Super-scaling

d)

Sequencing

55.

Two processors A and B have clock frequencies of 700 MHz and 800 MHz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction, which processor is faster?

a)

A

b)

B

c)

Both A and B take the same time

d)

Insufficient information

56.

Two processors A and B have clock frequencies of 2.2 GHz and 2.3 GHz respectively. Suppose A can execute an instruction with an average of 4 steps and B can execute with an average of 5 steps. For the execution of the same instruction, which processor is faster?

a)

A

b)

B

c)

Both A and B take the same time

d)

Insufficient information

57.

Two processors A and B have clock frequencies of 2.2 GHz and 1.8 GHz respectively. Suppose A can execute an instruction with an average of 5 steps and B can execute with an average of 3 steps. For the execution of the same instruction, which processor is faster?

a)

A

b)

B

c)

Both A and B take the same time

d)

Insufficient information

58.

The address of the instruction following the CALL instructions stored in _____

a)

Stack

b)

Program counter

c)

Heap

d)

Static memory

59.

In the CPU, what is the functionality of the control unit?

a)

To decode program instruction

b)

To perform logic operations o

c)

To store program instruction o

d)

To transfer data to primary storage

60.

Which representation is most efficient to perform arithmetic operations on the numbers?

a)

Sign-magnitude

b)

1's complement

c)

2's complement

d)

None of them

61.

When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____

a)

The higher order byte of the word

b)

The lower order byte of the word

c)

Can't say

d)

None of them

62.

Which of the following storages may have an associative access method?

a)

Main memory

b)

Cache

c)

Disks

d)

Virtual memory

63.

Using a direct mapping method for a memory of 32 blocks and a cache of 4 lines, how many bits are used for tag field?

a)

2

b)

3

c)

4

d)

5

64.

In the context of memory hierarchy which statement is correct?

a)

Greater memory capacity, faster access time

b)

Greater memory capacity, greater cost per bit

c)

Faster access time, greater cost per bit

d)

Faster access time, lower cost per bit

65.

__________ refers to whether memory is internal or external to the computer.

a)

Location

b)

Access

c)

Hierarchy

d)

Tag

66.

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.

a)

Access time

b)

Unit of transfer

c)

Capacity

d)

Memory ratio

67.

"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________.

a)

Sequential access

b)

Direct access

c)

Random access

d)

Associative

68.

individual blocks or records have a unique address based on physical location with __________.

a)

Associative

b)

Physical access

c)

Direct access

d)

Sequential access

69.

For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.

a)

Memory cycle time

b)

Direct access

c)

Transfer rate

d)

Access time

70.

The ________ consists of the access time plus any additional time required before a second access can commence.

a)

Latency

b)

Memory cycle time

c)

Direct access

d)

Transfer rate

71.

A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.

a)

Disk cache

b)

Latency

c)

Virtual address

d)

Miss

72.

A line includes a _________ that identifies which particular block is currently being stored.

a)

Cache

b)

Hit

c)

Tag

d)

Locality

73.

__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.

a)

Direct mapping

b)

Associative mapping

c)

Set associative mapping

d)

None of them

74.

When using the __________ technique all write operations made to main memory are made to the cache as well.

a)

Write back

b)

LRU

c)

Write through

d)

Unified cache

75.

One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly.

a)

RAM

b)

ROM

c)

EPROM

d)

EEPROM

76.

In a _________, binary values are stored using traditional flip-flop logic-gate configurations.

a)

ROM

b)

SRAM

c)

DRAM

d)

RAM

77.

A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it.

a)

RAM

b)

SRAM

c)

ROM

d)

Flash memory

78.

Adjacent tracks are separated by _________.

a)

sectors

b)

gaps

c)

pits

d)

heads

79.

Data are transferred to and from the disk in __________.

a)

tracks

b)

gaps

c)

sectors

d)

pits

80.

RAID level ________ has the highest disk overhead of all RAID types.

a)

0

b)

1

c)

3

d)

5

81.

The _________ contains logic for performing a communication function between the peripheral and the bus.

a)

I/O channel

b)

I/O module

c)

I/O processor

d)

I/O command

82.

The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices.

a)

cycle

b)

status reporting

c)

control and timing

d)

data

83.

An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________.

a)

I/O channel

b)

I/O command

c)

I/O controller

d)

device controller

84.

Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS.

a)

utility

b)

multitasking

c)

JCL

d)

logical address

85.

________ is when the processor spends most of its time swapping pages rather than executing instructions.

a)

Swapping

b)

Thrashing

c)

Paging

d)

Multitasking

86.

The OS maintains a __________ for each process that shows the frame location for each page of the process.

a)

kernel

b)

page table

c)

TLB

d)

logical address

87.

The operation _________ yields true if either or both of its operands are true.

a)

NOT

b)

AND

c)

NAND

d)

OR

88.

The unary operation _________ inverts the value of its operand.

a)

OR

b)

NOT

c)

NAND

d)

XOR

89.

A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals.

a)

gate

b)

decoder

c)

counter

d)

flip-flop