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WorksheetsComputer Architecture Quiz
Total questions: 89
Worksheet time: 45mins
The Small extremely fast, RAM's are call as_____?
Cache
Stack
Heaps
Registers
Which of the architecture saves memory?
Harvard
Von Neumann
Harvard & Von Neumann
None of them
During the execution of the instructions, a copy of the instructions is placed in the _____
HDD
RAM
Cache
Register
Which of these is a valid byte?
11011011
10022011
AA-AA-BB-BB
00-11-FF-F
The ALU makes use of _______ to store the intermediate results.
Accumulators
Registers
Heap
Stack
A source program is usually in _______
Assembly language
Machine level language
High-level language
Natural language
How many possible values can we have with 8 bits?
8
1 byte
256
127
The binary valua of the ASCII letter "c" is 01100011. Its decimal value is _____
123
100
45
99
Where does the CPU store its computations?
Registers
External Data Bus
Binary
Processor
Which memory device is genrally made of semiconductors?
Floppy disk
CDROM
DVD
RAM
_____ are numbers and encoded characters, generally used as operands.
Information
Stored values
Output
Data
The input devices can send information to the processor when _____
When the SIN status flag is set
When the data arrives regardless of the SIN flag
All of them
None of them
The ______ format is usually used to store data
All of them
Decimal
Hexadecimal
Octal
The 8-bit encoding format used to store data in a computer is ______
ASCII
EBCDIC
ANCI
UNICODE
The control unit controls other units by generating ___________
Control signals
Timing signals
Transfer signals
Command Signals
To reduce the memory access time we generally make use of ______
Heaps
Higher capacity RAM's
SDRAM's
Cache's
The time delay between two successive initiations of memory operation _______
Memory access time
Memory search time
Memory cycle time
Instruction delay
Which of the register/s of the processor is/are connected to Memory Bus?
PC
MAR
IR
Both PC and MAR
ISP stands for _________
Instruction Set Processor
Information Standard Processing
Interchange Standard Protocol
Interrupt Service Procedure
____ is used to choose between incrementing the PC or performing ALU operations.
Conditional codes
Multiplexer
Control unit
None of them
The registers, ALU and the interconnection between them are collectively called as _____
process route
information trail
information path
data
The first computer constructed using vaccum tubes was _____
EDVAC
ENIAC
EDIAC
IBM PC
_____ is not one of the four basic functions of a computer
Data processing
Data storage
Data movement
I/O processing
The second generation of computers based on _____
Vacuum tubes
Transistors
IC
VLSI
The third generation of computers based on _____
Vacuum tubes
Transistors
IC
VLSI
The binary representation of -7 is _____ o
0111
1001
1101
1011
What is the function of MAR?
Read a word from memory
Specify an address of memory
Contains the 8 bit opcode o
Store address of the next instruction
What is the function of MBR?
Read a word from memory
Specify an address of memory
Contains the 8 bit opcode
Store address of the next instruction
Which registers can interact with the secondary storage?
PC
IR
R1
MAR
The binary representation of -15 is _____
00100000
01000000
10000000
11110001
_____ is the binary representation of -1:
00000000
00001111
11110000
11111111
The registers and ALU are connected by using _____
Control path
Process route
Information path
Data path
If a processor clock is rated as 3 GHz then its clock period is _____
3.00*10^-10 sec
3.00*10^-9 sec
0.33*10^-10 sec
0.33*10^-9 sec
If a processor clock is rated as 1.8 GHz then its clock period is _____
5.55*10^-10 sec
5.55*10^-9 sec
0.55*10^-10 sec
55.5*10^-9 sec
The main virtue for using single Bus structure is ____________
Fast data transfers
Cost effective connectivity and speed
Cost effective connectivity and ease of attaching peripheral devices
None of them
ANSI stands for __________
American National Standards Institute
American National Standard Interface
American Network Standard Interfacing
American Network Security Interrupt
In multiple Bus organisation, the registers are collectively placed and referred as ______
Set registers
Register file
Register Block
Map registers
The ISA standard Buses are used to connect ___________
RAM and processor
GPU and processor
Harddisk and Processor
CD/DVD drives and Processor
Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?
A
B
A and B take the same time
Insufficient information
For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?
ISA
ANSA
Super-scalar
All of them
An optimizing Compiler does _________
Better compilation of the given piece of code
Takes advantage of the type of processor and reduces its process time
Does better memory management
None of them
When Performing a looping operation, the instruction gets stored in the ______
Registers
Cache
System Heap
System stack
The average number of steps taken to execute the set of instructions can be made to be less than one by following _______
ISA
Pipe-lining
Super-scaling
Sequential
Which method/s of representation of numbers occupies a large amount of memory than others?
Sign-magnitude
1's complement
2's complement
1's & 2's compliment
What is the maximum addressable memory of a 32-bit microprocessor with 24-bit address?
16 MB
16 Mbits
16 GB
16 Gbits
A complete microcomputer system consist of _____
Microprocessor
Memory
Peripheral equipment
All of them
CPU fetches the instruction pointed by____
MR
MAR
MBR
PC
The processing required for a single instruction is called an _____
Instruction processing
Instruction cycle
Memory instruction
Memory cycle
The fetched instruction is loaded into a register in the processor known as the _____
Memory
Kernel
Instruction register
SSD
The processor may perform some arithmetic or logic operation on data is _____
Data processing
Control
Processor
Data transferring
SDRAM stands for _____
Static dynamic random access memory
System dynamic random access memory
Synchronous dy
s _____
Data processing
Control
Processor
Data transferring
SDRAM stands for _____
Static dynamic random access memory
System dynamic random access memory
Synchronous dynamic random access memory
Syndrome dynamic random access memory
A processor performing fetch or decoding of different instruction during the execution of another instruction is called _____
Parallel Computation
Pipe-lining
Super-scaling
Sequencing
Two processors A and B have clock frequencies of 700 MHz and 800 MHz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction, which processor is faster?
A
B
Both A and B take the same time
Insufficient information
Two processors A and B have clock frequencies of 2.2 GHz and 2.3 GHz respectively. Suppose A can execute an instruction with an average of 4 steps and B can execute with an average of 5 steps. For the execution of the same instruction, which processor is faster?
A
B
Both A and B take the same time
Insufficient information
Two processors A and B have clock frequencies of 2.2 GHz and 1.8 GHz respectively. Suppose A can execute an instruction with an average of 5 steps and B can execute with an average of 3 steps. For the execution of the same instruction, which processor is faster?
A
B
Both A and B take the same time
Insufficient information
The address of the instruction following the CALL instructions stored in _____
Stack
Program counter
Heap
Static memory
In the CPU, what is the functionality of the control unit?
To decode program instruction
To perform logic operations o
To store program instruction o
To transfer data to primary storage
Which representation is most efficient to perform arithmetic operations on the numbers?
Sign-magnitude
1's complement
2's complement
None of them
When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____
The higher order byte of the word
The lower order byte of the word
Can't say
None of them
Which of the following storages may have an associative access method?
Main memory
Cache
Disks
Virtual memory
Using a direct mapping method for a memory of 32 blocks and a cache of 4 lines, how many bits are used for tag field?
2
3
4
5
In the context of memory hierarchy which statement is correct?
Greater memory capacity, faster access time
Greater memory capacity, greater cost per bit
Faster access time, greater cost per bit
Faster access time, lower cost per bit
__________ refers to whether memory is internal or external to the computer.
Location
Access
Hierarchy
Tag
For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.
Access time
Unit of transfer
Capacity
Memory ratio
"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________.
Sequential access
Direct access
Random access
Associative
individual blocks or records have a unique address based on physical location with __________.
Associative
Physical access
Direct access
Sequential access
For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.
Memory cycle time
Direct access
Transfer rate
Access time
The ________ consists of the access time plus any additional time required before a second access can commence.
Latency
Memory cycle time
Direct access
Transfer rate
A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.
Disk cache
Latency
Virtual address
Miss
A line includes a _________ that identifies which particular block is currently being stored.
Cache
Hit
Tag
Locality
__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.
Direct mapping
Associative mapping
Set associative mapping
None of them
When using the __________ technique all write operations made to main memory are made to the cache as well.
Write back
LRU
Write through
Unified cache
One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly.
RAM
ROM
EPROM
EEPROM
In a _________, binary values are stored using traditional flip-flop logic-gate configurations.
ROM
SRAM
DRAM
RAM
A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it.
RAM
SRAM
ROM
Flash memory
Adjacent tracks are separated by _________.
sectors
gaps
pits
heads
Data are transferred to and from the disk in __________.
tracks
gaps
sectors
pits
RAID level ________ has the highest disk overhead of all RAID types.
0
1
3
5
The _________ contains logic for performing a communication function between the peripheral and the bus.
I/O channel
I/O module
I/O processor
I/O command
The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices.
cycle
status reporting
control and timing
data
An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________.
I/O channel
I/O command
I/O controller
device controller
Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS.
utility
multitasking
JCL
logical address
________ is when the processor spends most of its time swapping pages rather than executing instructions.
Swapping
Thrashing
Paging
Multitasking
The OS maintains a __________ for each process that shows the frame location for each page of the process.
kernel
page table
TLB
logical address
The operation _________ yields true if either or both of its operands are true.
NOT
AND
NAND
OR
The unary operation _________ inverts the value of its operand.
OR
NOT
NAND
XOR
A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals.
gate
decoder
counter
flip-flop
