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WorksheetsComputer Architecture Quiz
Total questions: 97
Worksheet time: 54mins
What is the initial state of a process when it is admitted by the high-level scheduler, but not yet ready to execute?
New
Ready
Running
Halted
The chunks of a program, known as pages, could be assigned to available chunks of memory, known as frames, is called_____
Swapping
Partitioning
Paging
Virtual Memory
Segmentation
How does Boolean algebra contribute to the design of digital circuits?
It simplifies the implementation of desired functions
It helps in the analysis of economic data
It facilitates the design of analog circuits
It is primarily used for chemical engineering and physical engineering
When both inputs are 1, what is the result of a NAND gate?
0
1
2
Undefined
#NA
Express a sign integer number (+18) in the sign magnitude representation.
00010010
10010010
11110010
01110010
Why is it essential to use symbolic representation of machine instructions?
It makes machine instructions more human-readable and understandable
It reduces the overall complexity of computer systems and user programs
It minimizes the need for memory storage for the user programs
It enables fastest execution of high level language instructions
The hardware mechanism that allows a device to notify the CPU is called____
polling
interrupt
driver
controlling
What is a branch instruction?
The instructions that are used to divide a program into multiple subprograms
The instructions that have as one of its operands the address of the next instruction to be executed
The instructions that are used to pause the program
The instructions that are used to return to the beginning of the program
In MASM32, which OPCODE is used to compare two values?
COM
CMP
IF... ELSE
TEST
What is the role of the control unit in a processor?
The control unit's primary role is to perform arithmetic and logical operations within the processor, orchestrating the manipulation of data
The control unit only manages the flow of data between the CPU and external devices and does not play a significant role in executing instructions
The control unit is solely responsible for managing the flow of instructions from secondary storage to RAM and does not have a role in the internal operation of the CPU
The control unit in a processor directs and coordinates the execution of instructions, interpreting and managing the flow of operations within the CPU
How do data registers and address registers differ in some computer systems?
Address registers can be employed in calculating operand addresses, while data registers hold data.
Data registers are only used for stack-related operations
Data registers are used for indexed addressing, while address registers are used for data storage
Address registers are reserved for segmented addressing, while data registers are general-purpose
What is the main benefit of using ARM processors over other processors?
Low cost and low power consumption
Higher degree of multi-tasking
Lower error or glitches
Efficient memory management
Which statement is incorrect about RISC and CISC architecture?
CISC architecture is more convenient for programmers than RISC architecture.
CISC architecture has more operands in a instruction compared to RISC architecture.
CISC architecture has a more flexible instruction set than RISC architecture.
CISC architecture requires more general-purpose registers than RISC architecture.
What is the main benefit of using RISC over CISC?
RISC has more instructions and addressing modes than CISC
RISC has faster instruction execution and simpler instruction decoding than CISC
RISC has variable-length instruction formats and direct memory access than CISC
RISC has more registers and pipelines than CISC
What is the benefit of using a super-scalar organization over a scalar organization?
It increases the instruction throughput and improves the performance
It reduces the power consumption and the heat dissipation
It simplifies the instruction set and the compiler design
All of the mentioned
None of the mentioned
What does the term 'instruction-level parallelism' refer to in computer architecture?
The degree to which instructions in a program can be executed in parallel
The number of processor cores in a multi-core CPU with multiple resources
The complexity of the instruction set architecture
The length of an instruction cycle with high level programming language
To enhance performance in a superscalar processor, which method(s) should we apply?
Duplication of resources.
Out-of-order issue.
Renaming registers
All of the mentioned.
How many common classifications of parallel systems are there as proposed by Flynn?
2
3
4
5
Which write technique in which all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid.
Write through
Write back
Write around
No write allocate
How does multithreading improve the performance of a processor?
It increases the instruction-level parallelism by issuing multiple instructions from different threads in the same cycle
It increases the thread-level parallelism by executing multiple threads on different cores or processors
It increases the utilization of the processor resources by hiding the latency of long-latency events such as cache misses or branch mispredictions
All of the mentioned
Follow the Amdahl's law for multiprocessors, if only 10% of the code is inherently serial (f = 0.9), running the program on a multicore system with 4 processors, a performance gain (speedup factor) would be_____
307%
297%
317%
327%
Which cache is not a shared cache?
L4 cache
L3 cache
L2 cache
L1 cache
What is the significance of the program counter (PC) in the fetch phase of the instruction cycle?
The program counter (PC) is not used in the fetch phase, and its role is limited to tracking the number of instructions executed by the CPU
The program counter (PC) in the fetch phase holds the memory address of the next instruction to be fetched and executed
The program counter (P) is responsible for executing instructions and has no specific role during the fetch phase
The program counter (PC) is only relevant in multi-core processors and does not contribute to the fetch phase of the instruction cycle in single-core systems
Which write technique in which all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid.
Write through
Write back
Write around
No write allocate
Central processing unit (CPU) of IAS computer consists of
Main memory and ALU (arithmetic and logic unit)
ALU (Arithmetic and Logic Unit) and CU (Control Unit)
CU (Control Unit) and IO Module
Which component defines the system call interface to the operating system and facilitates binary portability?
Application Binary Interface
Application Programming Interface
Instruction Set Architecture
Central Processing Unit
The first generation of computers used _ for digital logic elements and memory?
Transistor
Integrated Circuits
Large-scale integration
Vacuum Tubes
The first generation of computers used _ for digital logic elements and memory?
Transistor
Integrated Circuits
Large-scale integration
Vacuum Tubes
For reads to and writes from main memory,________translates each virtual address into a physical address in main memory
MAR
MMU
Overlays
TLB
Accumulator
In the concept of Register Windows, how many register groups are there?
4
3
2
No distinction
Which of the following statements is part of the Von Newmann principle?
The computer uses a program counter to indicate the location of the next statement
Computer can control all operations with a single program
Computer memory is not addressable
Each instruction must have a memory area containing the address of the next instruction
What is the distinction between Computer Architecture and Computer Organization?
Computer Architecture is the way the system is structured, while Computer Organization is those attributes of a system that are visible to the user
Organization the Way The system is structure a system that are visible to the user, while Computer Computer Architecture is the way the system is structured
Computer Architecture and Computer Organization are the same
Computer Architecture is slower than Computer Organization
Which of the following are the four basic functions that a computer performs?
Data processing, Data storage, Data movement, Control
Data processing, Data storage, Data movement, Interrupt
Data processing, Data storage, Interrupt, Control
Data processing, Interrupt, Data movement, Control
Which one of four basic functions of computer describes the following statement? *The paths among components are used to move data from memory to memory and from memory through
Data storage
Data processing
Data movement
Control
During the development process of the computer, which of the following statements is false?
The second generation uses transistors
The first generation uses vacuum tubes
The fourth generation uses integrated circuit
The third generation uses transistor
What electronic component is used to govern operations such as fetching, decoding, and performing arithmetic operations executed by a processor?
Using a system clock
Using a quartz crystal
Using a analog to digital converter
Using a counter
The pulse rate in the ck system is known as the
ck cycle
ck speed
ck time
ck tick
Which register is the memory address register?
MAR
MBR
IR
PC
Which representation is most efficient to perform arithmetic operations on the signed integer numbers?
Sign-magnitude
2's complement
1's & 2's compliment
1's complement
What is true about IAS Memory Formats?
The memory of the lAS consists of 1000 storage locations (called words) of 32 bits each
Only data is stored in the memory
Both data and instructions are stored in the memory
Only instructions are stored in the memory
What is the most important characteristic of the Synchronous Bus?
Data is transmitted at the same time
The occurrence of one event on a bus follows and depends on the occurrence of a previous event.
The occurrence of events on the bus is determined by a clock
No common clock signal controlling operation
Which of the following memory devices has the lowest access speed?
ROM
Flash memory
Magnetic tape
HDD
Cache
Consider an expression: NOT (1111 1010) What is the result of this expression?
0000 1010
0000 0101
1111 0101
1111 1010
What is the primary purpose of cache memory in a computer system?
To store frequently used data for quick access
To store the operating system
To store user files and documents
To store the CPU registers
A set-associative cache consists of 64 lines, divided into four-line sets. 2*19 words main memory contains 4K blocks of 128 words each. How many bits are there in the tag field of the cache?
5
6
7
8
9
Why is cache design used in high-performance computing (HPC)? (Choose three correct answers)
Why is cache design used in high-performance computing (HPC)? (Choose three correct answers)
Because there is a significant speed gap between the processor and the internal memory in HPC.
Because applications in HPC often require a large bandwidth to support intensive data processing
Because power consumption can be a significant operational cost in HPC environments.
Because multiple processors are often working in parallel, caches provide a way to efficiently manage data required by these processors
How many bytes of data does each sector in the Winchester hard drive disk have?
128 bytes
256 bytes
512 bytes
1024 bytes
4096 bytes
What is correct about increasing performance and endurance?
Hard Disk-DRAM - NAND Flash - SRAM
Hard Disk - NAND Flash - DRAM - SRAM
NAND Flash - Hard Disk - SRAM - DRAM
Hard Disk - DRAM - NAND Flash - SRAM
With the hard disk data layout, the set of all the tracks in the same relative position on the platter, is called _____
Cylinder
Tracks
Inter-track gap
Sector
Consider a 5-drive, 200 Bytes-per-drive RAID array. What is the available data storage capacity for each of the RAID levels 5?
200 GBytes
400 GBytes
600 GBytes
800 GBytes
None of the mentioned
Consider a drive, 100 GBytes per-drive RAID array. What is the available data storage capacity for each of
400 GBytes
200 GBytes
300 GBytes
500 GBytes
What is incorrect about SSDs have the following advantages over HDDs?
Higher access times and latency rates: Over 10 times slower than the HDD.
Durability: Less susceptible to physical shock and vibration.
Longer lifespan: SSDs are not susceptible to mechanical wear
Lower power consumption: SSDs use considerably less power than comparable size HDDs.
Quieter and cooler running capabilities: Less space required, lower energy costs, and a greener enterprise.
Which registers can interact with the secondary storage?
MAR
PC
IR
RO
All of the mentioned
Consider an expression: A + (B.C) What expression is equal to the given expression?
(A + B).(A + C)
(A+B).C
A.(B+C)
NOT (A.(B+C))
Determine the address of the next instruction to be executed. Usually, this involves adding a fixed number to the address of the previous instruction.
Instruction fetch
Instruction operation decoding
Instruction address calculation
Operand fetch
Operand address calculation
For interrupts, all I/O modules share a common interrupt request line. When the processor senses an interrupt, it sends out an interrupt acknowledge. This signal propagates through a series of I/O modules until it gets to a requesting module. Which kind of interrupt technique is it?
Multiple interrupt lines
Software poll
Daisy chain
Bus arbitration
What role does an Application Programming Interface (API) play in software development?
It allows program access to hardware resources using high-level language libraries
It defines low-level machine instructions
It provides a standard for binary portability
It manages system resources for the operating system and machine language instructions
Which state indicates that a process is currently being executed by the processor?
Running
Ready
NewBorn
Halted
The task of subdivision is carried out dynamically by the OS and is known as ____
Scheduling
Memory management
Virtual Memory
All of the mentioned
Which of the following statements is incorrect about Translation Look-aside Buffer (TLB)?
The use of TLB eliminates the need for keeping a page table in memory
TLB only maintains a subset of the entries stored in the full memory-based page table
When there is a TLB miss the system needs to access the page table
A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory
(R1) = 01110110, (R2) = 11011111, the result of (R1) XOR (R2) is:
11011011
00010110
10101001
11001101
What is the output of a NOT gate when the
the result of (R1) XOR (R2) is:
11011011
00010110
10101001
11001101
What is the output of a NOT gate when the input is 0?
0
1
Undefined
2
Express an integer number +18 (using 8-bits length) in twos complement representation.
00010010
10010010
00001101
10011101
Which registers can be assigned to a variety of functions by the programmer?
Data registers
General purpose registers
Address registers
Condition codes (flags)
What are the most important general categories of data that machine instructions operate on?
Addresses, numbers, characters, and logical data
Text, images, and audio
Variables, functions, and arrays
Instructions, control signals, and registers
What is the output of Left Shift Operator << on (00011000<<2)?
01100000
11000000
00000110
00000011
Which addressing mode allows direct specification of the memory address within the instruction?
Direct
Indirect
Register Indirect
Displacement
Which of the following PDP series computers is known for its use of 12-bit instructions and a single general-purpose register, the accumulator?
PDP-8
PDP-10
PDP-11
PDP-6
In MASM32, which command is incorrect?
ADD EAX, a
ADD EAX, EBX
ADD a, EAX
ADD a, b
What is the primary function of the Arithmetic and Logic Unit (ALU) in a processor?
Perform actual computations and data processing
Control the movement of data and instructions
Act as an interface to the system bus
Manage the internal processor memory
The PC, IR, MAR, MBR registers belong to which of the following groups?
Control and Status Registers
User-Visible Registers
General Registers
Handle Registers
When considering the number of pipeline stages, what trade offs must be made in computer architecture?
Trade-offs between potential speedup and increased cost and delays
Trade-offs between software and hardware
Trade-offs between speed and efficiency
Trade-offs between branching and executing instructions with conditions
What does CISC stand for?
Complex Instruction Set Computer
Computer Instruction Set Complex
Complex Instruction Summarize Computer
Computer Instruction Summarize Complex
What is one of the advantages of using a register file in computer architecture?
Reduction in memory accesses, saving time
More efficient use of space due to dynamic adaptation
Efficient handling of both local and global variables
Easier management of cache residency
How does pipelining in a RISC architecture handle branch instruction?
By using NOOP instructions inserted by the compiler or assembler
By eliminating branch instructions from the instruction stream
By executing branch instructions in a separate pipeline
By delaying all instructions until branch instructions are executed
_____ is (are) determined by the number of instructions that can be fetched and executed at the same time (the number of parallel pipelines) and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions.
Instruction-level parallelism
Machine parallelism
Both instruction-level parallelism and machine parallelism
None of the mentioned
Which is the correct choice for the description: "A single machine instruction controls the simultaneous execution of a number of processing elements such as vector and array processors*?
Single instruction, single data (SISD)
Single instruction, multiple data (SIMD)
Multiple instruction, single data (MISD)
Multiple instruction, multiple data (MIMD)
What is one advantage of Nonuniform Memory Access (NUMA) over Uniform Memory Access (UMA)?
NUMA provides each processor with its own local memory, reducing memory access times
NUMA allows all processors to access the same memory location simultaneously
NUMA is easier to implement than UMA
NUMA provides limited memory capacity
What is the most common mapping technique used in cache memory in modern computers?
Direct Mapping
Fully Associative
Set Associative
None of the mentioned
What technique is used in cache memory in modern computers?
Direct Mapping
Fully Associative
Set Associative
None of the mentioned
Which of the following statements is NOT part of the Von Neumann principle?
Computers can operate according to a stored program
The computer uses a program counter to indicate the location of the next statement
A computer's memory is addressable
Each statement must have a memory area containing the address of the next instruction
Regarding the ALU(Arithmetic Logic Unit), besides basic arithmetic operations, what operations can it perform? (choose two correct answers)
It handles logical operations such as AND, OR, XOR, NOT.
It handles data transfer operations like MOVE, GO, JUMP.
It handles decoding operations after an instruction is fetched.
It handles bit shifting operations like multi and div operations by powers of two.
Select the main technology applied in each computer generation
1 - D ; 2 - C ; 3 - B
1 - A ; 2 - C ; 3 - D
1 - A ; 2 - B ; 3 - C
1 - D ; 2 - B ; 3 - C
The instruction, which adds 1 to the value in a memory location, has five stages: fetch opcode (four cycles), fetch operand address (three cycles), fetch operand (three cycles), add 1 to operand (three cycles), and store operand (three cycles). An interrupt sends request at beginning of fetch operand stage. How many cycles does the processor enter the interrupt processing cycle?
6
7
8
9
10
What is the function of the bus system in the computer?
Extend the communication function of the computer
Connect components in the computer
Control peripherals
Transform signals in the computer
All of the mentioned
What is the special feature of Memory Cache?
Allows faster access than DRAM memory
Memory cache is outboard storage memory
Allows faster access than CPU registers
Fixed memory - Read Only Memory
Has a larger capacity than HDD
A set-associative cache consists of 64 lines, divided into four-line sets. 2^19 - words main memory contains 4K blocks of 128 words each. How many bits are there in the tag field of the cache?
5
6
7
8
9
Which one of the following is an invalid about RAM?
Both static and dynamic RAMs are volatile; that is, power must be continuously supplied to the memory to preserve the bit values
A dynamic memory cell is simpler and smaller than a static memory cell.
Both static and dynamic RAMs requires the supporting refresh circuitry
SRAMs are somewhat faster than DRAMs
In error correcting code (single ECC), how many bits are used to correct one bit in 8-bit data?
4
5
6
7
The speed of data delivery is your main concern when configuring a RAID drive for a Media Streaming Server. This server has two hard disks installed. What type of RAID should you install, and what type of data will be stored on Disk 1 and Disk 2?
RAID 0 - Disk 1 (Stripe) and Disk 2 (Stripe)
RAID 0 - Disk 1 (Mirror) and Disk 2 (Mirror)
RAID 1 - Disk 1 (Stripe) and Disk 2 (Stripe)
RAID 1 - Disk 1 (Mirror) and Disk 2 (Mirror)
In terms of performance, what is the main advantage of a solid state drive over a magnetic disk?
A solid state drive has faster access time, lower latency, and higher reliability
A solid state drive has larger capacity, lower power consumption, and lower cost
A solid state drive has better compatibility, longer lifespan, and higher security
A solid state drive has none of the mentioned advantages over a magnetic disk
Assume that a truth table: X Y OUTPUT 1 1 1 1 0 1 0 1 1 0 0 0. Which basic operator matches the table above?
AND
OR
NAND
NOR
What is an interrupt vector?
Part of memory which contains the addresses of interrupt handlers
A signal an I/O device sends to CPU
What is an interrupt vector?
A. Interrupt-Driven I/O involves the CPU
in every data transfer, while DMA by-
passes the CPU and transfers data di-
rectly between I/O device and memory
B. Interrupt-Driven I/O requires special
hardware and software support, while
DMA does not need any additional com-
ponents
C. Interrupt-Driven 1/O is suitable for
small and frequent data transfers, while
DMA is suitable for large and infrequent data transfers
D. All of the mentioned
