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Embedded system

Total questions: 30

Worksheet time: 15mins

Name
Class
Date
1.

Which one of the following is a real time operating system?



a)

a) RTLinux

b)

b) VxWorks

c)

c) Windows CE

d)

d) All of the mentioned

2.

Real time systems must have ____________


c)

a)

a) preemptive kernels

b)

b) non preemptive kernels

c)

C) preemptive kernels or non preemptive kernels

d)

d) neither preemptive nor non preemptive kernels

3.

Remote Procedure Calls are used ____________



a)

a) for communication between two processes remotely different from each other on the same system

b)

b) for communication between two processes on the same system

c)

c) for communication between two processes on separate systems

d)

d) none of the mentioned

4.

A Process Control Block(PCB) does not contain which of the following?



a)

a) Code

b)

b) Stack

c)

c) Bootstrap program

d)

d) Data

5.

The initial program that is run when the computer is powered up is called __________



a)

a) boot program

b)

b) bootloader

c)

c) initializer

d)

d) bootstrap program

6.

Which of the following condition is required for a deadlock to be possible?



a)

a) mutual exclusion

b)

b) a process may hold allocated resources while awaiting assignment of other resources

c)

c) no resource can be forcibly removed from a process holding it

d)

d) all of the mentioned

7.

Message passing system allows processes to __________



a)

a) communicate with each other without sharing the same address space

b)

b) communicate with one another by resorting to shared data

c)

c) share data

d)

d) name the recipient or sender of the message

8.

ARM stands for

a)

a )Advanced Risc Machine

b)

b) Advanced Risc Microprocessor

c)

c )Advanced Risc Microcontroller

d)

d )None of above

9.

The address system supported by ARM systems is/are ___________



a)

a) Little Endian

b)

b) Big Endian

c)

c) X-Little Endian

d)

d) Both Little & Big Endian

10.

The banked registers are used for ______



a)

a) Switching between supervisor and interrupt mode

b)

b) Extended storing

c)

c) Same as other general purpose registers

d)

d) None of the mentioned

11.

The standard SRAM chips are costly as _________



a)

a) They use highly advanced micro-electronic devices

b)

b) They house 6 transistor per chip

c)

c) They require specially designed PCB’s

d)

d) None of the mentioned

12.

. The main virtue for using single Bus structure is ____________



a)

a) Fast data transfers

b)

b) Cost effective connectivity and speed

c)

c) Cost effective connectivity and ease of attaching peripheral devices

d)

d) None of the mentioned

13.

Which of the following is a part of the AMBA protocol family?




a)

A) PCIe

b)

B) USB

c)

C) AHB

d)

D) I2C

14.

A "bootloader" in an embedded system is used for:




a)

A) Loading web pages

b)

B) Loading and executing the main application software

c)

C) Formatting the memory

d)

D) Cooling down the processor

15.

In RISC architecture, most instructions are executed in:




a)

A) 10 or more clock cycles

b)

B) A single clock cycle

c)

C) Two clock cycles

d)

D) Multiple variable clock cycles

16.

What is the name of the ARM register R13 commonly used as?




a)

A) Program Counter (PC)

b)

B) Stack Pointer (SP)

c)

C) Link Register (LR)

d)

D) Status Register

17.

What does the CPSR register in ARM contain?




a)

A) Address of next instruction

b)

B) Stack pointer

c)

C) Processor status flags and mode bits

d)

D) Interrupt vector

18.

What are the three basic stages of the ARM7 pipeline?




a)

A) Decode, Execute, Store

b)

B) Fetch, Decode, Execute

c)

C) Load, Execute, Write

d)

D) Fetch, Load, Store

19.

Which of the following ARM versions introduced a 5-stage pipeline?




a)

A) ARM7

b)

B) ARM9

c)

C) ARM11

d)

D) ARM Cortex-M0

20.

What is the main purpose of cache memory in a processor?




a)

A) Store permanent data

b)

B) Increase instruction count

c)

C) Store backup files

d)

D) Reduce average memory access time

21.

What is Tightly Coupled Memory (TCM) in ARM architecture?




a)

A) External memory module

b)

B) Special memory with direct processor access for deterministic behavior

c)

C) Swappable memory module

d)

D) A type of cache

22.

What is the primary function of the Memory Protection Unit (MPU)?




a)

A) Handle virtual memory

b)

B) Encrypt memory

c)

C) Control access to memory regions

d)

D) Compress memory usage

23.

What is the main function of the Memory Management Unit (MMU)?




a)

A) Cache instruction results

b)

B) Translate virtual addresses to physical addresses

c)

C) Schedule CPU instructions

d)

D) Encrypt memory pages

24.

Which of the following is NOT a typical function of a coprocessor?




a)

A) Floating-point arithmetic

b)

B) Memory management

c)

C) Instruction fetching

d)

D) Cryptographic processing

25.

What does the ARM instruction SUB R1, R2, R3 do?




a)

A) Adds R2 and R3

b)

B) Subtracts R1 from R2

c)

C) Subtracts R3 from R2 and stores result in R1

d)

D) Stores R3 in R2

26.

What does the ARM instruction MOV R0, R1, LSL #2 do?




a)

A) Adds R0 and R1

b)

B) Moves R1 to R0 and multiplies by 2

c)

C) Moves R1 to R0 after shifting left by 2 bits

d)

D) Swaps R0 and R1

27.

What is the result of MOV R2, R1, ROR #4 if R1 = 0xF0000000?




a)

A) Rotates R1 4 bits right and stores in R2

b)

B) Adds 4 to R1

c)

C) Shifts left 4 bits

d)

D) Multiplies R1 by 4

28.

What does the ARM instruction B label do?




a)

A) Adds the value of label to the Program Counter (PC)

b)

B) Branches to the address specified by label (unconditional)

c)

C) Moves the label into a register

d)

D) Compares label with a register value

29.

In ARM, what does the BGE instruction check before branching?




a)

A) Branch if signed value is greater than or equal (based on N and V flags)

b)

B) Branch if less than or equal (based on Z flag)

c)

C) Branch if overflow occurred

d)

D) Branch if negative value

30.

What does the instruction "LDR R0, [R1, #4]" do in ARM architecture?

  • .

a)
  • A) Load the value from memory address stored in R1 into register R0, with an offset of 4.

b)
  • B) Load the value from memory address stored in R1 into register R0

c)
  • C) Load register R0 with the value in R1.

d)
  • D) Store the value of R0 at memory address R1.