WorksheetsCHAPTER 1 OVERVIEW OF INTEGRATED CIRCUITS DESIGN
Total questions: 51
Worksheet time: 26mins
Name
Class
Date
1.
When was the integrated circuit industry formed?
a)
The 1940s
b)
The 1950s
c)
The 1960s
d)
The 1970s
2.
Which semiconductor device accounts for over 96% of transistors in integrated circuit design?
a)
BJT
b)
FinFET
c)
MOSFET
d)
CMOS
3.
Which layout file format is used to link the designer and manufacturer?
a)
GDS
b)
CIF
c)
PDK
d)
SPICE
4.
What is the definition of PDK?
a)
A system containing all components, information, and properties used in integrated circuit design.
b)
An integrated circuit design software.
c)
An integrated circuit simulation tool.
d)
An integrated circuit manufacturing process.
5.
Which process uses the Czochralski technique to create a silicon rod?
a)
Silicon refining
b)
Crystal growth
c)
Wafer formation
d)
Chemical vapor deposition
6.
How many main sectors is the integrated circuit industry divided into?
a)
2
b)
3
c)
4
d)
5
7.
Which company below specializes in integrated circuit design?
a)
TSMC
b)
Samsung Electronics
c)
Broadcom
d)
SMIC
8.
What is the GDS file format used for in the integrated circuit design process?
a)
Checking circuit correctness
b)
Simulating circuit parameters
c)
Creating layout for integrated circuit manufacturing
d)
Analyzing circuit models
9.
What does PDK stand for?
a)
Process Design Kit
b)
Physical Design Kit
c)
Prototype Design Kit
d)
Production Design Kit
10.
What components does a PDK include?
a)
Technology Setup, Design Rule Decks, Simulation Model, Verification, Installation
b)
Design Tools, Simulation Software, Verification Hardware, Production Equipment
c)
Layout Files, Simulation Files, Verification Data, Manufacturing Data
d)
Library Files, Process Files, Layout Files, Verification Files
11.
What is the SPICE model used for in integrated circuit design?
a)
Designing layout
b)
Simulating circuits
c)
Physical verification
d)
Manufacturing integrated circuits
12.
The BSIM model was developed to replace which model?
a)
SPICE level 1, 2, 3 models
b)
EKV model
c)
PSP model
d)
Philips model
13.
Which model is most commonly used in the current integrated circuit industry?
a)
SPICE model
b)
EKV model
c)
BSIM3v3 model
d)
PSP model
14.
The wafer manufacturing process begins with refining which grade of silicon?
a)
Metallurgical-grade silicon (MGS)
b)
Electronic-grade silicon (EGS)
c)
Polycrystalline silicon
d)
Monocrystalline silicon
15.
What is the Czochralski process used for?
a)
Creating polycrystalline silicon
b)
Creating monocrystalline silicon
c)
Refining metallurgical-grade silicon
d)
Producing electronic-grade silicon
16.
What is the diameter of the largest wafer currently in use?
a)
200 mm
b)
300 mm
c)
450 mm
d)
600 mm
17.
Why are wafers typically round instead of square or rectangular?
a)
Easier to manufacture and handle
b)
Maximizes wafer area utilization
c)
Higher silicon quality
d)
Reduces manufacturing costs
18.
Which process in integrated circuit manufacturing involves forming an SiO2 layer on the silicon surface?
a)
Diffusion
b)
Thermal oxidation
c)
Ion implantation
d)
Sputtering
19.
What is ion implantation used for in integrated circuit manufacturing?
a)
Creating an SiO2 insulating layer
b)
Introducing impurities into silicon
c)
Forming a metal layer on the silicon surface
d)
Creating the layout for integrated circuits
20.
At which university was the EKV model developed?
a)
University of California, Berkeley
b)
EPFL (Ecole Polytechnique Fédérale de Lausanne)
c)
University of Pennsylvania
d)
Stanford University
21.
Which of the following is not a step in the integrated circuit manufacturing process?
a)
Oxidation
b)
Photolithography
c)
Sputtering
d)
Networking
22.
Which process is used to create thin films on the wafer surface?
a)
Oxidation
b)
Photolithography
c)
Chemical vapor deposition (CVD)
d)
Diffusion
23.
In integrated circuit manufacturing, ion implantation helps control what?
a)
Thickness of the SiO2 layer
b)
Concentration and location of impurities in silicon
c)
Size
d)
Shape of dies on the wafer
24.
Photolithography involves using what to transfer the design onto the wafer surface?
a)
Ultraviolet light, mask, and photoresist
b)
X-rays, mask, and photoresist
c)
Laser, mask, and photoresist
d)
Infrared light, mask, and photoresist
25.
In photolithography, what happens to positive photoresist when exposed to ultraviolet light?
a)
It becomes more soluble and easier to dissolve
b)
It becomes less soluble and harder to dissolve
c)
It polymerizes and becomes harder
d)
It becomes conductive
26.
Wafers are produced from raw silicon material with the highest purity level of what?
a)
Metallurgical-grade silicon (MGS)
b)
Electronic-grade silicon (EGS)
c)
Polycrystalline silicon
d)
Monocrystalline silicon
27.
Digital integrated circuit design uses which hardware description languages?
a)
Verilog, VHDL
b)
SPICE, PSPICE
c)
MATLAB, Simulink
d)
C++, Java
28.
Chemical vapor deposition (CVD) is used to create which layers on the wafer surface?
a)
Insulating and metal layers
b)
Impurity layers
c)
Monocrystalline silicon layers
d)
Polycrystalline silicon layers
29.
Which process helps restore the silicon crystal lattice after ion implantation?
a)
Oxidation
b)
Annealing
c)
Photolithography
d)
Chemical vapor deposition (CVD)
30.
The PSP model combines the best features of which models?
a)
Philips model version 11 and SP model
b)
BSIM and EKV models
c)
SPICE and EKV models
d)
Philips and SPICE models
31.
In integrated circuit manufacturing, the SiO2 layer is typically created by which method?
a)
Dry and wet oxidation
b)
Chemical vapor deposition (CVD)
c)
Ion implantation
d)
Sputtering
32.
Silicon wafers are sliced from what after crystal growth using the Czochralski process?
a)
Polycrystalline silicon
b)
Monocrystalline silicon
c)
Metallurgical-grade silicon
d)
Electronic-grade silicon
33.
The BSIM4 model better models which effects characteristic of MOSFETs?
a)
Intrinsic capacitance effects
b)
Drain current effects
c)
Parasitic effects
d)
Surface effects
34.
Which integrated circuit manufacturing process uses a particle accelerator?
a)
Diffusion
b)
Ion implantation
c)
Oxidation
d)
Sputtering
35.
Dry oxidation uses which oxidizing agent?
a)
H2O
b)
O2
c)
NH3
d)
HCl
36.
Which process checks the compatibility between the layout and the circuit schematic?
a)
DRC (Design Rule Check)
b)
LVS (Layout Versus Schematic)
c)
PEX (Parasitic Extraction)
d)
ERC (Electrical Rule Check)
37.
In photolithography, ultraviolet light is used to do what?
a)
Create the SiO2 layer
b)
Create the metal layer
c)
Pattern the photoresist
d)
Create the integrated circuit layout
38.
In photolithography, what happens to negative photoresist when exposed to ultraviolet light?
a)
It becomes more soluble and easier to dissolve
b)
It becomes less soluble and harder to dissolve
c)
It polymerizes and becomes harder
d)
It becomes conductive
39.
Ion implantation helps control what in integrated circuit manufacturing?
a)
Thickness of the SiO2 layer
b)
Concentration and location of impurities in silicon
c)
Size
d)
Shape of dies on the wafer
40.
Projection lithography has what characteristic compared to other photolithography methods?
a)
Lower accuracy
b)
Creates larger features
c)
Uses a projector to shrink the mask image onto the wafer
d)
Uses X-rays instead of ultraviolet light
41.
One advantage of ion implantation over diffusion is what?
a)
Occurs at higher temperatures
b)
Easier to control and more precise
c)
Uses less energy
d)
Creates thicker impurity layers
42.
In integrated circuit manufacturing, sputtering is used to create what on the wafer surface?
a)
Insulating layer
b)
Metal layer
c)
Impurity layer
d)
Monocrystalline silicon layer
43.
In photolithography, the main steps to create a pattern include what?
a)
Coating with photoresist, exposure, development, etching
b)
Coating with photoresist, ion implantation, development, etching
c)
Coating with photoresist, annealing, development, etching
d)
Coating with photoresist, oxidation, development, etching
44.
In integrated circuit manufacturing, what is the role of the SiO2 layer?
a)
Insulating layer
b)
Metal layer
c)
Impurity layer
d)
Monocrystalline silicon layer
45.
Chemical vapor deposition (CVD) is used to create which layers on the wafer surface?
a)
Insulating and metal layers
b)
Impurity layers
c)
Monocrystalline silicon layers
d)
Polycrystalline silicon layers
46.
Which of the following is not a model used in integrated circuit design?
a)
SPICE
b)
EKV
c)
PSP_baseline
d)
CMOS
47.
Which process checks the compatibility between the layout and the circuit schematic?
a)
DRC (Design Rule Check)
b)
LVS (Layout Versus Schematic)
c)
PEX (Parasitic Extraction)
d)
ERC (Electrical Rule Check)
48.
Thermal oxidation typically occurs at what temperature range?
a)
200-400°C
b)
500-700°C
c)
900-1200°C
d)
1300-1500°C
49.
The BSIM model uses an approach based on what operational characteristics?
a)
Physical
b)
Electromagnetic
c)
Chemical
d)
Engineering
50.
Chemical mechanical polishing (CMP) is used for what purpose?
a)
Creating an insulating layer
b)
Smoothing and planarizing the wafer surface
c)
Creating a metal layer
d)
Ion implantation
51.
Which process is used to clean the wafer surface?
a)
Oxidation
b)
Photolithography
c)
Plasma cleaning
d)
Ion implantation
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