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Worksheets20EC214 - Quiz-1
Total questions: 10
Worksheet time: 3mins
The condition for linear region of NMOS device is ___________
Vgs lesser than Vt
Vgs greater than Vt
Vds lesser than Vgs
Vds greater than Vgs
As source drain voltage increases, channel depth
increases
decreases
logarithmically increases
exponentially increases
If the gate is given sufficiently large charge, electrons will be attracted to
drain region
switch region
bulk region
channel region
Which of the following statement is true?
charging time > discharging time
charging time and discharging time are not related
charging time = discharging time
charging time < discharging time
The architecture used to design VLSI is ____________
system on a device
system on a chip
single open circuit
system on a circuit
Physical and electrical specification is given in _____________
functional design
system design
architectural design
logic design
NMOS fabrication process is carried out in _____
thin wafer of multiple crystals
thick wafer of multiple crystals
thin wafer of a single crystal
thick wafer of a single crystal
In a MOSFET, the polarity of the inversion layer is the same as that of the __________
Charge on the gate electrode
Minority carriers in the drain
Majority carriers in the substrate
Majority carriers in the source
What is the transition point of an inverter?
Vdd
0.5 Vdd
0.25 Vdd
2 Vdd
Mobility of proton or hole at room temperature is _____
650 cm2/V sec
460 cm2/V sec
240 cm2/V sec
500 cm2/V sec
