WorksheetsComputer I/O and DMA Quiz
Total questions: 115
Worksheet time: 58mins
DMA stands for:
Direct Management Access
Direct Memory Application Access
Direct Memory Access
Direct Mainboard Administration
Characteristics of multi-level centralized bus arbitration:
Peripheral devices are connected to a single bus request line
Devices are connected to the bus arbitration unit with a single wire
Each peripheral device has a separate bus request line
Peripheral devices are connected to different bus request lines
Which statement about programmed I/O is incorrect?
The peripheral device is the active entity in data exchange
The peripheral device is the passive entity in data exchange
When executing a program with an I/O instruction, the CPU controls data exchange with the peripheral device
Using I/O instructions in the program to exchange data with ports
An important feature of an asynchronous bus is:
It has a common clock signal controlling operations
Data is transmitted simultaneously
It lacks a common clock signal controlling operations
Data is transmitted asynchronously
Which statement about block DMA is correct?
Data is transmitted whenever the bus is free
Data is transferred in blocks, and DMA returns the bus to the CPU after the entire block is transferred
The CPU is temporarily suspended during each bus cycle
Data is transmitted discontinuously in bytes
How many methods are there to identify interrupt modules?
4 methods
1 method
3 methods
2 methods
Which statement about serial I/O is correct?
Multiple bits are transmitted at once
It is fast
It requires multiple data transmission lines
It requires a converter from parallel to serial data and vice versa
Which of the following components is part of a peripheral device?
Signal converter
Peripheral device status/control register
Data buffer register
I/O ports
The main components in an I/O system are:
Data input devices and data output devices
Peripheral devices and I/O modules
Data conversion devices
Data transmission devices
In which bus arbitration method are peripheral devices connected to different bus request lines?
Multi-level centralized bus arbitration
Single-level centralized bus arbitration
Centralized bus arbitration
Decentralized bus arbitration
Which statement about the software polling method for determining interrupt modules is incorrect?
The CPU checks multiple I/O modules simultaneously
I/O processing speed is fast
The CPU performs software polling of each I/O module sequentially
The order of polling is the priority order
A modem is a type of peripheral device:
Machine-to-machine communication
Communication
Human-to-human communication
Human-to-machine communication
Which I/O control method requires the CPU to frequently check the status of the peripheral device?
Interrupt-driven I/O
Direct Memory Access I/O
None of the above
Programmed I/O
Compared to a synchronous bus, an asynchronous bus has the feature that:
It makes controlling computer operations easier
Designing the bus system is easier
It is difficult to exploit manufacturing technology advancements in bus system design
If one master-slave pair operates slowly, the next pair is unaffected
The data bus in a computer is:
Unidirectional for each line but bidirectional for the entire bus
Unidirectional
Bidirectional for each line
Variable width
Which of the following components belongs to the I/O module?
System bus
Status/control register
Data converter
Data buffer
A printer is a type of peripheral device:
Machine-to-machine communication
Human-to-human communication
Human-to-machine communication
Communication
Which statement about transparent DMA is correct?
When the DMAC does not use the bus, the CPU uses it
When the CPU does not use the bus, DMA is performed
The CPU and DMAC do not use the bus alternately
The CPU is forced by the DMAC to yield the bus
The system bus of a computer includes:
Data bus and control bus
Data bus and address bus
Data bus
Data bus, address bus, and control bus
When should a synchronous bus be used?
To maximize CPU processing time utilization
When bus cycles need to vary with each pair of data-exchanging devices
When most operations have processing times that are multiples of the bus cycle
When the system has many devices with significantly different speeds
What is the function of the expansion bus in a computer?
The transmission path between the CPU and intermediate support chips
The transmission path between processor blocks
Connecting the I/O system to the processor
Connecting the processor to main memory and cache memory
Which statement about DMA I/O is correct?
It is controlled directly by the CPU for data exchange
It adds a hardware module on the bus
It consumes CPU time
It is implemented by software
Which parameter characterizes the data transfer rate on a bus?
All three: bandwidth, width, frequency of the bus
Bandwidth of the bus
Frequency of the bus
Width of the bus
How many address lines does the IBM PC bus have?
20 lines
16 lines
32 lines
24 lines
Which bus connects the processor to main memory?
Processor bus
Peripheral bus
Processor internal bus
System bus
Which statement about parallel I/O is incorrect?
Transmitting bits sequentially
Transmitting multiple bits simultaneously
Fast speed
Requiring multiple data transmission lines
Which statement about parallel I/O is correct?
Slow speed
Fast speed
Requiring few data transmission lines
Requiring a converter from parallel to serial data and vice versa
Which statement about DMA data exchange is correct?
The CPU participates in data exchange
It is suitable for small data exchange (1 or 2 bytes)
The DMAC operates based on peripheral device demand
It is suitable for large block data exchange
What is the function of bus arbitration?
Resolving memory allocation issues for peripheral device operations connected to the bus
Controlling the processor to perform data exchange operations with peripheral devices connected to the bus
Resolving processor allocation issues for operations
Resolving bus ownership contention
Which statement about programmed I/O is correct?
It has a complex circuit design for data exchange
It is the fastest data exchange method
It has a complex and fastest circuit design for data exchange
It is the simplest data exchange method
Which statement about parallel I/O is incorrect?
Transmitting multiple bits simultaneously
Requiring few data transmission lines
Fast speed
Requiring multiple data transmission lines
Which statement about parallel I/O is correct?
Transmitting bits sequentially
Requiring few data transmission lines
Requiring a converter from parallel to serial data and vice versa
Requiring multiple data transmission lines
A Network Interface Card (NIC) is a type of peripheral device:
Communication
Human-to-human communication
Machine-to-machine communication
Human-to-machine communication
Which statement about block DMA is incorrect?
The CPU yields the entire bus to the DMAC
The CPU is not forced to temporarily suspend each bus cycle
Data is transmitted discontinuously in groups of 2 bytes
The D
Which component does not belong to the I/O module?
Data buffer register
Status/control register
I/O ports
Data buffer
Which of the following components is part of a peripheral device?
Data buffer register
I/O ports
Data buffer
Peripheral device status/control register
Which parameter indicates the number of bytes transferred through the bus in a unit of time?
Width of the bus
Frequency of the bus
All three: bandwidth, width, frequency of the bus
Bandwidth of the bus
Which component can act as a bus master?
Both CPU and I/O chips can act as bus masters
Only a single designated I/O chip can act as bus master
Only the CPU can act as bus master
Only I/O chips can act as bus masters
A scanner is a type of peripheral device:
Human-to-human communication
Human-to-machine communication
Machine-to-machine communication
Communication
What does the DMA mechanism allow?
Direct data transfer between main memory and I/O modules
Direct data transfer between peripheral devices
Direct data transfer between memory and CPU registers
Direct data transfer between components within the memory system
In which bus arbitration method is the bus usage division handled by a single bus arbitration unit?
Decentralized or centralized bus arbitration
Centralized bus arbitration
No bus arbitration
Decentralized bus arbitration
What is the function of the System Bus in a computer?
Connects the microprocessor to the main memory, L3 cache memory and I/O coupling controllers
Is the transmission line between blocks of the microprocessor
Transmission line between CPU and intermediate support chips
Connect the input and output system to the microprocessor
With the hardware polling method (in determining the interrupt module), which of the following statements is false?
The order of connecting I/O modules in series determines the priority order of I/O modules
The system has an interrupt request line (INTR) connected from the I/O modules to the CPU
The system has many interrupt request lines with specified priority levels
Which of the following characteristics is not a characteristic of a synchronous bus?
Bus period remains unchanged for all pairs of devices exchanging data
All operations are performed in time intervals that are multiples of the Bus period
Data exchange between devices requires a handshake signal
The system is timed intermittently
What is the function of the Bus system in a computer?
Changing the signal format in the computer
Link components in the computer
Expand your computer's communication functions
Control peripheral devices
What is the function of the microprocessor bus in a computer?
Is the transmission line between blocks of the microprocessor
Transmission path between CPU and L2 Cache
Connect the input and output system to the microprocessor
Connects the processor to main memory
For serial input and output connections, which of the following statements is false?
Transmit bits one at a time
A converter from parallel to serial data or/and vice versa is required
Requires few data lines
Transmit multiple bits at once
How many data lines does the IBM Pc bus have?
16 lines
6 lines
8 lines
10 lines
Methods for determining interrupt modules include
Using multiple interrupt request lines, software polling, hardware polling, using interrupt controller
Using multiple interrupt request lines, software polling, hardware polling, taking up CPU
Using multiple interrupt request lines, software polling, hardware polling, taking up memory
Polling by software, polling by hardware, takes up CPU, takes up memory
Characteristics of centralized Bus arbitration:
The Bus arbitration unit is located at the center of the computer
The division of Bus usage rights is undertaken by a single Bus arbitration unit
The Bus arbitration unit also owns the Bus
The division of Bus usage rights is done by the peripheral devices themselves
With the input/output method using DMA, which of the following statements is false?
The CPU and DMAC combine to control data exchange
This is the process of exchanging data between the I/O module and memory
Completely controlled by DMAC for data exchange
The CPU does not interfere with the data exchange process
In the case of using a synchronous bus, if an operation has a completion time of 3.2 cycles, in how many cycles will it actually be performed?
4.2
3
4
3.2
With the interrupt output method, which of the following statements is correct?
Is a method handled entirely by hardware
CPU is an object object in data exchange
Is a processing method using both hardware and software
Is a completely software processing method
The width of the Bus is determined by:
Bus data line number
Byte digital data is transmitted in a unit time
Digital data Bits are transmitted in a unit time
Number of components connected to the Bus
The functions of peripheral devices are:
Collect information put inside the computer
Convert data between inside and outside the computer
Transfer data between the computer and the real world
Intermediate storage data component
Which I/O control method requires that when the CPU receives a ready signal from a peripheral device, it will have to temporarily stop the work being done to exchange data with the peripheral device?
There is no method
Program input/output method
Direct memory access I/O method
I/O method by interrupt
The address bus in the computer is:
Bus has variable width
Bidirectional bus for each line
One-way bus
The bus is one-way for each line but is two-way for the entire bus
With the DMA input/output method, which of the following statements is correct?
Is a method directly controlled by the CPU in data exchange
Is the fastest method of data exchange between CPU and peripheral devices
Is a method implemented by software
Is a non-CPU controlled method of data exchange
In which type of Bus arbitration does the division of Bus usage rights not require a separate Bus arbitration unit?
Referee Bus focuses
Bus arbitration focuses on many levels
Referee Bus is not focused
The Bus referee focuses on one level
With the interrupt input and output method, which of the following statements is false?
The CPU must wait for the ready state of the peripheral device by checking in the program
The CPU does not have to wait for the ready state of the peripheral device
The I/O module interrupts the CPU when it is in the ready state
Peripheral devices are active objects in data exchange
Why is the synchronous bus more widely used in practice than the asynchronous bus?
Systems using synchronous buses are easier to design
Easy to take advantage of technological advances
Allows flexible change of bus cycle
Make good use of CPU processing time
For cyclic DMA type, which of the following statements is correct?
When memory is free, DMAC uses the Bus
DMAC uses Bus completely
CPU uses Bus completely
CPU and DMAC alternate using the Bus
With the multiple interrupt request line method (in determining the interrupt module), which of the following statements is correct?
The CPU must have different interrupt request lines for each I/O module
The CPU has multiple interrupt request lines for an I/O module
The number of input/output modules is quite large
The CPU has only one interrupt request line for I/O modules
For serial input and output connections, which of the following statements is false?
Slow speed
Fast speed
Requires few data lines
A converter from parallel to serial data or/and vice versa is required
Which of the following is a component of the input/output module?
System bus (system bus)
Data converter
Data buffer
Input/output ports
Keyboard is a type of peripheral device:
Human-machine communication
Person-to-person communication
Machine-machine communication
Communication
On what frequency does the IBM PC bus operate?
4.67Khz
4.67Mhz
4.77Khz
4.77Mhz
For the input/output control method, which of the following is not a characteristic of interrupt input/output?
CPU directly controls input and output
The CPU must wait for the I/O module
CPU is a passive component
There is a combination of hardware and software (hardware: causes CPU interrupt, software: data exchange)
Which of the following components is not a peripheral device?
Signal converter
Data buffer
Control logic block
Input/output ports
Which input/output control method does not require the CPU to directly control the data exchange process?
I/O method by interrupt
Direct memory access I/O method
There is no method
Program input/output method
Bus frequency characterizes:
Memory allocation speed for computer components
Speed controls the components of the computer
Data transmission speed on Bus
Speed of resource distribution in the computer
The control bus in a computer is:
Bidirectional bus for each line
Bus has variable width
One-way bus for each line, two-way for the entire bus
One-way bus
Which of the following components is not part of the input/output module?
Input/output ports
Status/control register
Data buffer register
Data converter
An optical drive is a type of peripheral device:
Machine-machine communication
Human-machine communication
Person-to-person communication
Communication
For DMA-type data exchange, which of the following statements is correct?
CPU participates in the data exchange process
This is a completely software exchange method
This is an exchange method using both hardware and software
This is a completely hardware exchange method
Which bus in the computer is responsible for being the transmission line between the CPU and L2 Cache memory?
Peripheral bus
Processor bus
Bus in the microprocessor
System bus
In the case of using an asynchronous Bus, if an operation has a completion time of 3.2 cycles, in how many cycles will it actually be performed?
4
3.2
4.2
3
What is the function of the Bus in a computer processor?
Transmission line between CPU and intermediate support chips
Is the transmission line between blocks of the microprocessor
Connect the input and output system to the microprocessor
Connects the processor to main memory
With the input/output method using DMA, which of the following statements is false?
After completing the data exchange process, DMAC sends a CPU interrupt signal to indicate the end of DMA
Before controlling, DMAC must ask the CPU for permission
This is a method with fast data exchange speed
This is a method with slow data exchange speed
Which parameter of the Bus indicates its line?
Bus width
All 3 bandwidth, width, frequency of the Bus
Bus bandwidth
Bus frequency
It is not possible to connect a peripheral device directly to the system bus because (please point out the incorrect statement):
Data in the computer is in the form of binary numbers, while data in peripheral devices is in the form of physical signals (light, sound, ...)
There exist a variety of peripheral devices that differ in operating principles, data formats, and operating speeds, so the processor cannot control all of these devices.
Manufacturers cannot manufacture devices that connect directly between the processor and peripherals
All peripherals operate slower than the processor and RAM
What are the important characteristics of the synchronous bus?
Data is transmitted simultaneously
Data is not transmitted simultaneously
There is a common clock signal that controls the operation
There is no common clock signal controlling the operation
For parallel input and output connections, which of the following statements is false?
Transmit multiple bits at once
Fast speed
A converter from parallel to serial data or/and vice versa is required
Needs multiple data lines
For serial input and output connections, which of the following statements is correct?
Transmit multiple bits at once
Transmit bits one by one sequentially
Fast speed
Needs multiple data lines
With the program input and output method, which of the following statements is correct?
Is a method completely processed by hardware
This is the data exchange method with the fastest and most complex circuit design
Is a method completely processed by software
Is a processing method using both hardware and software
Characteristics of decentralized bus arbitration with multibus:
The division of Bus usage rights does not require a separate Bus arbitration unit
The division of Bus usage rights is done by the peripheral devices themselves
The Bus arbitration unit is not centrally located on the computer
The Bus arbitration unit also owns the Bus
With the interrupt input and output method, which of the following statements is correct?
Is a method completely processed by hardware
Peripheral devices are active objects in data exchange
Is a method completely processed by software
CPU is the active object in data exchange
For parallel input and output connections, which of the following statements is correct?
Transmit multiple bits at once
Transmit bits one at a time
Requires few data lines
A converter from parallel to serial data or/and vice versa is required
For serial input and output connections, which of the following statements is correct?
Transmit multiple bits at once
Fast speed
Requires few data lines
Needs multiple data lines
Which bus in a computer is responsible for being the transmission line between blocks of the processor?
Bus in the microprocessor
System bus
System bus
Processor bus
For the cyclic DMA type, which of the following statements is false?
DMAC only uses a certain number of Bus cycles
DMAC uses Bus completely
CPU does not use the Bus completely
Data is not transmitted continuously
In some processors there is an I/O address space, so which of the following components are the I/O addresses attached to?
Each I/O address is associated with an I/O data buffer register
Each I/O address is associated with a peripheral device
Each I/O address is associated with an I/O module
Each I/O address is associated with an I/O port
Which of the following is a component of the input/output module?
System bus (system bus)
Data buffer
Data converter
Data buffer register
Characteristics of single-level centralized Bus arbitration:
Peripheral devices share the same line allowing the use of the Bus
Devices connect to the Bus arbitration unit with a single wire
Peripheral devices sharing the same bus request line
Each peripheral device has its own Bus request line
Screen is a type of peripheral device:
Machine-machine communication
Human-machine communication
Person-to-person communication
Communication
Which of the following components is not a peripheral device?
Signal converter
Data buffer
Control logic block
Peripheral device control/status register
With the input/output method using DMA, which of the following statements is false?
When DMAC has completed control data exchange, it does not need to notify the CPU
Add hardware module on Bus
When DMAC is active it occupies the Bus
The CPU cedes power to the DMAC to control data exchange between the I/O module and the memory
Basic operations in the input and output system
Receive data and transmit data
Converts data from physical form to digital form
Controls data converters
Data input and data output
Which bus in a computer is responsible for connecting input and output devices to the processor?
System bus
Bus in the microprocessor
Expansion bus
Processor bus
What is the DMA mechanism?
Control peripheral devices through memory
Control the memory system via peripheral devices
Direct memory access
Direct peripheral access
Compared to asynchronous bus, synchronous bus has the following characteristics:
Controlling computer operations is more difficult
Easy to take advantage of advances in manufacturing technology in bus manufacturing
Controlling computer operations is easier
Bus system design is more difficult
In what cases should asynchronous bus be used?
When the system has many devices with very small speed differences
Requires easy control of computer operations
Almost every operation has a processing time equal to a multiple of the Bus cycle
When the system has many devices with very different speeds
Which of the following buses is a one-way bus?
Data bus between processor and memory
Address bus
Control bus
Data bus inside the microprocessor
For serial input and output connections, which of the following statements is false?
Requires few data lines
A converter from parallel to serial data or/and vice versa is required
transmits bits one at a time
Needs multiple data lines
A hard drive is a type of peripheral device:
Machine-machine communication
Human-machine communication
Person-to-person communication
Communication
With the software polling method (in determining the interrupt module), which of the following statements is correct?
Fast input/output processing speed
CPU checks multiple input/output modules at the same time
The CPU executes software that asks each input and output module in turn
The order of priority is not fixed
How many lines does the IBM Pc bus have?
52 lines
42 lines
62 lines
32 lines
There are the following types of DMA data exchange:
Block DMA, Cyclic DMA, Transparent DMA
Array DMA, block DMA, one-time DMA
Periodic DMA, Half DMA, Transparent DMA
Array DMA, Cyclic DMA, Transparent DMA
Bus bandwidth is determined by:
Number of Bits transferred through the Bus in a unit of time (sec)
Number of Bytes transferred through the Bus in a unit of time (sec)
Number of Bits transferred through the Bus in one clock cycle
Number of Bytes transferred through the Bus in one clock cycle
For DMA-type data exchange, which of the following statements is correct?
This is the fastest exchange method
This is a slow exchange method
This method is suitable for exchanging small sized data (1 or 2 bytes)
CPU participates in the data exchange process
How many types of peripheral devices are there?
2 types
3 types
4 types
5 types
Which of the following buses is a bidirectional bus for each signal line?
Address bus for peripherals
Data bus
Control bus
Address bus for memory
One of the characteristics of the synchronous bus is:
The general clock signal frequency varies depending on system conditions
All operations are performed in time intervals that are multiples of the Bus period
Bus period changes with each pair of devices exchanging data
Data is transmitted continuously during every Bus cycle
There are three input/output control methods as follows:
I/O by interrupt, by CPU access, by operating system
Input/output by program, by system, by DMA
I/O by interrupt, by CPU access, by DMA
Input/output by program, by interrupt, by DMA
In which type of Bus arbitration do peripheral devices share the same Bus request line?
The Bus referee focuses on one level
Bus arbitration focuses on many levels
Referee Bus is not focused
Referee Bus focuses
