WorksheetsPCB Design Situational MCQs - Advanced to Expect
Total questions: 40
Worksheet time: 20mins
Your high-speed clock signal is exhibiting jitter. You suspect PCB layout. What’s the probable cause?
Clock routed next to analog lines
Clock routed with matched impedance
Clock routed in a straight line
Clock routed on internal layer
During EMC testing, your PCB emits excessive noise. What advanced layout fix should be applied?
Add thermal vias
Use continuous ground plane under high-speed signals
Increase track width
Increase silkscreen contrast
You observe signal reflections on a 50Ω transmission line. What’s the best corrective measure?
Terminate line with matching resistor
Add capacitive loads
Reduce PCB thickness
Increase track spacing
A microstrip trace is routed with abrupt impedance changes. What will most likely occur?
Improved bandwidth
Minimal signal distortion
Reflections and signal degradation
EMI immunity
Your 8-layer PCB has poor signal integrity. Which strategy helps most?
Stack-up optimization with signal-reference pairs
Add thermal reliefs
Add extra silkscreen
Route power over signal layers
You experience coupling between clock and reset lines. What’s a solid mitigation approach?
Add filtering capacitor
Increase spacing and route on different layers
Increase trace width
Increase PCB thickness
Your analog section shows noise induced from digital circuits. What PCB practice helps?
Use common ground plane
Physically isolate analog and digital sections
Share decoupling capacitors
Reduce analog trace width
When designing DDR memory routing, which layout aspect is crucial?
Blind via usage
Length matching for data and address lines
Increasing copper thickness
Avoiding silkscreen
A polygon pour around an RF circuit worsens performance. Why?
Acts as antenna and causes coupling
Increases impedance
Helps shielding
Reduces thermal resistance
In high-speed designs, what is the risk of stubs in signal routing?
Increased power efficiency
Signal reflection and resonance
Reduced trace length
Lower impedance
You used a copper pour under an inductor. What may occur?
Improved inductance
Magnetic field distortion and noise
Lower ESR
Increased Q factor
For a sensitive analog ADC, what’s the ideal grounding strategy?
Use digital ground
Star ground with separate analog and digital returns
Use ground loop
Connect analog ground to shield only
The PCB simulation shows a power plane resonance at 300 MHz. What should you do?
Reduce copper thickness
Add bypass capacitors with multiple values
Increase trace impedance
Use narrower traces
You placed decoupling caps far from IC VCC pins due to layout constraints. What is the result?
Better ripple rejection
Ineffective high-frequency filtering
Thermal stability
Increased loop area
Your PCB fails thermal tests due to heat concentration in a corner. What’s an advanced fix?
Use copper pours connected to thermal vias and heat sinks
Increase trace spacing
Move silkscreen text
Increase board size
For a switching regulator, where should the feedback trace be routed?
Along the power input
Through the ground plane
Isolated from high-switching areas
Next to the inductor
You routed a USB 3.0 signal pair with excessive layer transitions. What is the risk?
EMI reduction
Signal integrity degradation
Lower capacitance
Longer propagation delay only
You designed a PCB with thermal pads under QFNs but forgot via stitching. Result?
No issue
Heat build-up and failure
Lower thermal resistance
Increased efficiency
An RF signal trace was routed with inconsistent width. What does this affect?
Trace length only
EMI tolerance
Characteristic impedance, causing mismatch
Signal filtering
In high-density designs, what’s the best way to manage fanout from BGA packages?
Use through-hole vias
Use microvias and via-in-pad
Rotate the BGA
Move decoupling caps farther
You're designing a PCIe Gen4 interface and observe eye diagram collapse. What is a critical layout factor to optimize?
Differential pair color coding
Via stub length and layer transitions
Silkscreen misalignment
Trace copper pour
In an RF PCB at 5 GHz, you notice performance degradation due to substrate properties. What do you modify?
Change copper weight
Switch to low-Dk, low-loss laminate like Rogers
Increase silkscreen contrast
Use heavier soldermask
You’re designing an ultra-compact medical PCB that fails in thermal cycling. What’s the likely culprit?
Long net lengths
Improper use of CTE-mismatched materials
Low copper weight
Wide spacing between vias
Your board passes in simulation but fails EMI compliance at 400 MHz harmonics. What advanced remedy is best?
Add high-frequency LC filters at IOs
Thicker PCB substrate
Reduce soldermask thickness
Remove decoupling capacitors
For GHz-range clock signal, what design rule is critical when routing through multiple layers?
Controlled trace spacing
Minimize return path discontinuity and use backdrilling
Use wide traces
Increase solder pad size
While designing an 18-layer board, you observe signal integrity issues. What's a key design consideration?
Random via placement
Even symmetry in layer stack-up and return path planning
Larger board outline
Avoiding blind vias
Your high-voltage PCB design is arcing in field trials. What layout principle was likely ignored?
Thermal vias
IPC-2221 creepage and clearance rules
Use of ground pours
Increasing pad sizes
A 2.4 GHz antenna performs poorly on a multilayer board. What may be wrong?
Missing silkscreen
Inadequate ground clearance below antenna
Copper pour under digital IC
Unused vias on the board
You’re routing a mixed-signal board with audio and switching regulators. What should you avoid?
Placing analog and digital grounds together
Using shared decoupling caps
Mixing power and ground planes
Routing analog traces near switching nodes
An expert design contains split ground planes. What is a risk during return current flow?
Reduced power integrity
Ground bounce and unexpected EMI
Thermal resistance drop
Better signal path
While designing an HDI board, signal vias consume space in fine-pitch BGAs. What's a solution?
Increase board size
Use stacked microvias with via-in-pad
Move to thicker laminate
Skip decoupling capacitors
An RF front-end design fails during OTA (Over-The-Air) testing. What advanced layout trick helps?
Place GND stitching vias every λ/20 along antenna ground
Increase signal trace width
Use split GND planes
Increase pad diameter
You’re facing 3rd harmonic distortion in a power amplifier PCB. What layout issue is suspect?
Long RF trace with impedance discontinuity
Small thermal vias
Missing solder paste
Wide ground plane
In a space-constrained power PCB, you observe heat buildup. What's an advanced thermal solution?
Embedded copper coin or metal core
Enlarged silk pad
Increased spacing
Blind vias only
Your DDR5 design is showing eye diagram closure. What layout factor is critical at expert level?
Signal and clock length mismatch
Reference plane stitching under routing
Controlled impedance of routing
All of the above
On a power delivery network, low-frequency ringing is seen. Which layout strategy helps?
Bulk capacitance placed close to power source
Remove all ferrite beads
Use wide traces
Skip stitching vias
A multilayer board has current loops causing EMI. How can layout fix this?
Keep signal and return path tightly coupled on adjacent layers
Use thinner copper
Increase trace spacing
Add more components
What is the best way to reduce common-mode noise in differential pairs?
Use common-mode chokes
Route them far apart
Reduce trace width
Add decoupling capacitors
An expert PCB uses backdrilled vias. What is the purpose?
Reduce stub reflections at high-speed signals
Improve thermal performance
Reduce power plane resistance
Increase drill accuracy
You observe SI degradation on Layer 3 of a 12-layer board. Which expert-level diagnostic is best?
TDR (Time Domain Reflectometry)
Thermal imaging
Capacitance check
ESR testing
