WorksheetsSystem and CPU Architecture, 8051 and ARM
Total questions: 30
Worksheet time: 15mins
Name
Class
Date
1.
In Von Neumann architecture, both data and instructions:
a)
Use separate memory units
b)
Use the same memory and bus
c)
Are stored in CPU registers
d)
Are not stored at all
2.
What is a key limitation of Von Neumann architecture?
a)
Expensive hardware
b)
Complex programming model
c)
Von Neumann bottleneck due to shared bus
d)
Too many instruction sets
3.
Which architecture uses separate buses for data and instructions?
a)
RISC
b)
Von Neumann
c)
Harvard
d)
ARM
4.
Which of the following best describes RISC architecture?
a)
Complex instructions with fewer lines of code
b)
Fewer instructions executed rapidly
c)
Instructions that perform multiple tasks
d)
No need for a control unit
5.
In CISC architecture, an instruction can:
a)
Be executed in one clock cycle
b)
Perform multiple operations in a single instruction
c)
Only perform arithmetic operations
d)
Use only 8-bit data
6.
Which processor type is known for microprogrammed control units?
a)
RISC
b)
ARM
c)
CISC
d)
Harvard
7.
A primary benefit of RISC architecture is:
a)
Fewer registers
b)
Simple hardware design and pipelining
c)
Higher instruction decoding time
d)
Slower performance per instruction
8.
ARM processors are based on:
a)
CISC
b)
Von Neumann
c)
Harvard
d)
RISC
9.
What is the major design goal of CISC processors?
a)
Hardware simplification
b)
Minimal memory use
c)
Reduced number of instructions per program
d)
Software-controlled pipelines
10.
RISC instructions typically have:
a)
Variable-length format
b)
Complex addressing modes
c)
Uniform instruction length
d)
In-built microcode
11.
Which of the following best explains the 'Von Neumann Bottleneck'?
a)
Power limitation in CPUs
b)
Instruction execution lag due to serial access of code/data
c)
Cache synchronization delay
d)
Control unit and ALU conflict
12.
The 8051 is based on which memory architecture?
a)
Harvard
b)
Von Neumann
c)
RISC
d)
CISC
13.
Which of the following is true for Harvard architecture?
a)
One bus for instructions and data
b)
Fewer registers required
c)
Simultaneous access to instruction and data
d)
Designed only for RISC
14.
The ALU is responsible for:
a)
Instruction fetch
b)
Managing I/O ports
c)
Performing logic and arithmetic operations
d)
Handling stack memory
15.
In 8051, which register holds the return address during subroutine calls?
a)
DPTR
b)
SP
c)
PC
d)
Stack
16.
Which of the following is an 8-bit register in 8051?
a)
PC
b)
DPTR
c)
ACC
d)
Program Memory
17.
How many general-purpose working registers (R0–R7) are in one register bank of the 8051?
a)
4
b)
7
c)
8
d)
16
18.
What is the function of the MOV A, #55H instruction?
a)
Move value from register A to memory
b)
Copy value from memory to A
c)
Load immediate value 55H into accumulator
d)
Increment the accumulator
19.
The 8051's Program Counter (PC) is:
a)
8-bit and stores data
b)
16-bit and points to the next instruction
c)
Part of ALU
d)
Bit-addressable
20.
What is the purpose of the Stack Pointer (SP) in 8051?
a)
Address control register
b)
Stores loop counters
c)
Tracks top of the stack
d)
Stores interrupt vector
21.
Which addressing mode uses the format MOV A, 30H in 8051?
a)
Immediate
b)
Register Indirect
c)
Direct
d)
Indexed
22.
Which instruction is used for register indirect addressing in 8051?
a)
MOV A, R1
b)
MOV A, #20H
c)
MOV A, @R1
d)
MOV A, 20H
23.
What does the instruction CPL A do in 8051?
a)
Complements the program counter
b)
Clears accumulator
c)
Complements accumulator bits
d)
Copies accumulator to port
24.
What is the default reset value of the Stack Pointer (SP) in 8051?
a)
00H
b)
08H
c)
07H
d)
FFH
25.
Which flag in PSW is set if the result of an arithmetic operation is zero?
a)
CY
b)
OV
c)
P (Parity)
d)
No such flag
26.
What is the use of MOVX instruction in 8051?
a)
Move data between registers
b)
Move external memory data
c)
Exchange register values
d)
Move bit-level data
27.
Which of the following is not a feature of RISC?
a)
Few instruction formats
b)
High-level instructions like string copy
c)
Register-based instructions
d)
Simplified decoding
28.
CISC processors are more dependent on:
a)
Compiler efficiency
b)
Simpler control units
c)
Microcode and hardware-level complexity
d)
Reduced pipeline stages
29.
Which type of processor is generally easier to pipeline?
a)
CISC
b)
ARM
c)
RISC
d)
Harvard
30.
Von Neumann architecture executes instructions:
a)
Using dual memory for instructions and data
b)
With a parallel ALU
c)
Sequentially from shared memory
d)
Through stack registers only
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