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WorksheetsVLSI unit-1
Total questions: 40
Worksheet time: 30mins
Name
Class
Date
1.
What will be the output of the following code?
module test;
reg [3:0] a = 4'b1010;
initial $display("%d", a);
endmodule
a)
10
b)
1010
c)
4
d)
Error
2.
What is the value of out after this always block executes?
always @(a or b)
begin
out = a &b;
end
a)
Bitwise AND of a and b
b)
Logical AND of a and b
c)
Sum of a and b
d)
Bitwise OR of a and b
3.
What does the always block below describe?
always @(posedge clk)
q <= d;
a)
Combinational logic
b)
Asynchronous latch
c)
D Flip-Flop
d)
Counter
4.
What will be the output y if a=1 and b=1 in the following?
assign y = ~(a & b);
a)
1
b)
0
c)
X
d)
Z
5.
Which of the following data types is NOT supported in Verilog?
a)
reg
b)
wire
c)
int
d)
bit_vector
6.
Which of the following is used to simulate delay in Verilog?
a)
@
b)
#
c)
$
d)
%
7.
Which of the following describes a blocking assignment in Verilog?
a)
<=
b)
->
c)
=
d)
<<=
8.
In Verilog, what kind of assignment does assign perform?
a)
Sequential
b)
Blocking
c)
Continuous
d)
Procedural
9.
What is the default value of a reg type in Verilog if not initialized?
a)
1
b)
0
c)
X
d)
Z
10.
Which keyword is used to stop simulation in Verilog?
a)
Halt
b)
Exit
c)
$end
d)
$finish
11.
What will be the value of x after simulation of the following Verilog code?
reg [3:0] x;
initial begin
x = 4'b1010;
x = x >> 1;
x = x << 2;
end
a)
4'b0001
b)
4'b1000
c)
4'b0100
d)
4'b0000
12.
In Verilog, what is the result of the following conditional expression?
assign y = (4'b101x == 4'b1011);
a)
1
b)
0
c)
X
d)
z
13.
Consider the code:
reg [3:0] a = 4'b1001;
reg [3:0] b = 4'b1x01;
wire c;
assign c = (a == b);
What is the value of c?
a)
1
b)
0
c)
X
d)
Z
14.
The keyword parameter in Verilog is used to:
a)
Declare a wire
b)
Declare a variable that can change at runtime
c)
Declare a compile-time constant
d)
Declare a port
15.
Consider:
initial begin
a = 0;
#5 a = 1;
end
always @(a)
$display("a changed to %b", a);
How many times is $display executed?
a)
0
b)
1
c)
2
d)
Depends on simulation time
16.
In Verilog, the following module creates what logic?
assign y = ~a & b | a & ~b;
a)
XOR
b)
OR
c)
AND
d)
NAND
17.
The following code creates what kind of logic?
assign y = a ? b : c;
a)
AND
b)
OR
c)
Latch
d)
2:1 Mux
18.
The expression x <= x + 1; in an always block implies:
a)
Sequential increment
b)
Combinational logic
c)
Blocking increment
d)
Infinite loop
19.
Consider:
assign y = a ^ a;
What is the value of y?
a)
1
b)
0
c)
X
d)
Z
20.
Which of the following simulates a ripple carry adder?
a)
Gate-level full adder instantiation in sequence
b)
Parallel adder using always block
c)
assign y = a + b;
d)
Procedural case statement
21.
Which of the following correctly simulates an edge-triggered D flip-flop?
a)
assign q = d
b)
always @* q = d
c)
always @(posedge clk) q <= d
d)
always @(negedge clk) q = ~d
22.
How many times is "Hello" printed in this code?
integer i;
initial
begin
for (i = 0; i < 4; i = i + 1)
$display("Hello");
end
a)
3
b)
4
c)
5
d)
Infinite
23.
Which operator is used for replication in Verilog?
a)
{}
b)
[ ]
c)
{{}}
d)
{{}*}
24.
In Verilog, assign #5 y = a + b; means:
a)
Add 5 after 5 time units
b)
Assign immediately
c)
Assign result after 5 units
d)
Delay evaluation and assignment indefinitely
25.
Which modeling style offers most accurate timing simulation?
a)
Algorithmic
b)
Gate Level
c)
RTL
d)
Behavioral
26.
In the expression {a,b}, what does it represent?
a)
Concatenation
b)
Replication
c)
Reduction
d)
Range operator
27.
What is the output of the reduction operator?
assign z = ^4'b1011;
a)
1
b)
0
c)
X
d)
Z
28.
What data type is used for continuous assignments?
a)
reg
b)
real
c)
wire
d)
int
29.
Which of the following is a legal Verilog keyword?
a)
always
b)
trigger
c)
launch
d)
register
30.
What will 4'b0011 << 1 result in?
a)
4'b0010
b)
4'b0110
c)
4'b0001
d)
4'b1100
31.
The purpose of a test bench in Verilog is to:
a)
Synthesize the circuit
b)
Implement a gate
c)
Verify the design
d)
Create a delay
32.
Which of the following is a valid way to write a 4-bit binary number in Verilog?
a)
4b1010
b)
4'd10
c)
4'b1010
d)
b4'1010
33.
Which symbol is used for single-line comments in Verilog?
a)
/*
b)
//
c)
%%
d)
#
34.
What is the size of the wire declared as wire [3:0] data;?
a)
2
b)
3
c)
4
d)
5
35.
What is the correct way to declare a 16-bit register?
a)
reg data[16];
b)
reg [15:0] data;
c)
wire [15:0] data;
d)
bit data[15:0];
36.
In gate-level modeling, what happens if more than one gate drives the same wire without resolution logic?
a)
Simulation error due to multiple drivers
b)
The output takes the latest value
c)
The output gets resolved automatically
d)
Only one driver will be considered
37.
In behavioral modeling, what is the difference between blocking and non-blocking assignments?
a)
Blocking is for parallel execution, non-blocking is for sequential
b)
Blocking executes sequentially, non-blocking executes concurrently
c)
Blocking executes in delta time, non-blocking in simulation time
d)
No difference in simulation
38.
Which of the following statements best describes the use of initial and always blocks?
a)
Both run only once
b)
initial runs once, always runs repeatedly
c)
Both execute simultaneously forever
d)
Both are used in gate-level modeling
39.
reg [3:0] a = 4'b1001;
initial begin
a = a << 1;
end
a)
4'b0010
b)
4'b0011
c)
4'b1010
d)
4'b1011
40.
What would be the result of this switch-level statement?
nmos (out, in, ctrl);
a)
Connects in to out when ctrl is 0
b)
Connects in to out when ctrl is 1
c)
Always conducts
d)
Only conducts during positive edge
Reset
