WorksheetsElectrical FE Study Session 6
Total questions: 10
Worksheet time: 30mins
What is the state of Q and Ǭ for the D flip-flop before the third rising edge of B?
Q = 0, Ǭ = 1
Q = 0, Ǭ = 0
Q = 1, Ǭ = 1
Q = 1, Ǭ = 0
Which of the following represents the state table for the state machine shown below?
A PLC program written in ladder logic has inputs A, B, and C. Assume that input A is HIGH 80% of the time, input B is HIGH 50% of the time and input C is HIGH 60% of the time. Which programming configuration, if any, will ensure the rung is evaluated most quickly?
Option 1
Option 2
Option 3
Option 4
All options are equally fast
Simplify the following expression to its simplest form using Boolean algebra:
AC + ABC + ABC
ABC + AC
AC + AB + AC + AC + BC
AC + AB + BC
Determine the minimized Sum of Product expression for the logic function given by k-map:
AC + A ̅ + ABC ̅
AC + A + AB ̅C
AB + AC + ABC
A ̅B ̅ + A ̅C ̅ + ABC
Determine the minimized Sum of Product expression for the logic function given by k-map:
B
B ̅
ABC
A ̅B ̅C ̅
For the given PLA circuit, the logical output Y can be expressed as:
AB + ABC ̅ + A ̅B ̅C
ABC + A ̅B ̅C
AB + A ̅B ̅C
A ̅B ̅C + A ̅B
A T (toggle) flip-flop is shown. The truth table that represents this circuit is:
Option A
Option B
Option C
Option D
Simplify the following expression to its simplest form using Boolean algebra:
AB
AB + CD + EF
ABCDEF
(A + B)(C + D)(E + F)
FPGA stands for:
Field-Programmable Gate Array
Factory-Programmable Gate Array
Functional Programmable Gate Array
Fast Programmable Gate Array
