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Worksheets

Vriddhi 2k25

Total questions: 20

Worksheet time: 10mins

Name
Class
Date
1.
  1. Choose the correct expansion of the acronym VLSI.

a)

Vast Logic System Integration

b)

Very Low Scale Integration

c)

Very Large Scale Integration

d)

Variable Large Scale Integration

2.

Identify the logic family that combines NMOS and PMOS transistors.

a)

BiCMOS

b)

CMOS

c)

PMOS

d)

TTL

3.

Arsenic and Boron are doped(added) into pure Si to change its ________________

a)

Physical Property

b)

Dimensions

c)

Electrical property

d)

Valence Electrons

4.

Boron having 3 valence electrons creats P type Semiconductor by _____________ Electrons

a)
Accepting
b)

Donating

c)

Passing

d)

None of the above

5.

Arsenic having 5 valence electrons creats N type Semiconductor by _____________ Electrons

a)

Accepting

b)

Passing

c)

Donating

d)

None of the above

6.

MOS transistor structure is ____________

a)

symmetrical

b)

non symmetrical

c)

semi symmetrical

d)

pseudo symmetrical

7.

Choose the correct ratio for pull-up to pull-down in a CMOS inverter to achieve equal rise and fall times.

a)

1:1

b)

2:1

c)

1:2

d)

3:1

8.

In CMOS logic circuit the p-MOS transistor acts as:

Pull down network

a)

Pull down network

b)

Pull up network

c)

Load

d)

Short to ground

9.

In a CMOS logic circuit, the n-MOS transistor acts as:

Pull down the network

a)

Pull down network

b)

Pull up network

c)

Load

d)

Short to ground

10.

Doubling the amount of transistors in every 18 months, is known as

a)


Gordan's Law

b)

Moore's Law

c)


Moor's law

d)


None of these

11.

A circuit that has 10k~1Billion transistor on chip and is still growing is termed as

a)

MSI

b)

SSI

c)

VLSI

d)

LSI

12.

Miniaturization lead to

a)

Lower Power Consumption

b)

Cheaper Production

c)

Faster Performance

d)

All of the above

e)

None of the above

13.

Key factors demonstrating Moore's Law are:

a)

Clock frequency

b)

Transistor Density

c)

Processor Performance

d)

Power Efficiency

e)

All of the above

14.

Modern processors use transistors with feature sizes below ________ nanometers

a)

5

b)

3

c)

100

d)

1000

15.

Terminals of CMOS

a)

Emitter, Base and Collector

b)

Gate, Source and Drain

c)

NPN and PNP

d)

nMOS and pMOS

16.

MOS is a ___________ device

a)

Voltage and Current Controlled

b)

Current Controlled

c)

Voltage Controlled

d)

Current and Voltage Controlled

17.

PMOS passes ________ and NMOS passes __________

a)

Good 0 Good 0

b)

Good 0, Good 1

c)

Good 1, Good 0

d)

Good 1, Good 1

18.

Pull Up Network(PUN) is constructed using _________

a)

NMOS

b)

PMOS

c)

Both a and b

d)

none

19.

Pull Down Network(PDN) is constructed using _________

a)

NMOS

b)

PMOS

c)

Both a and b

d)

none

20.

CMOS network is constructed using _________

a)

NMOS

b)

PMOS

c)

Both a and b

d)

none