WorksheetsVriddhi 2k25
Total questions: 20
Worksheet time: 10mins
Choose the correct expansion of the acronym VLSI.
Vast Logic System Integration
Very Low Scale Integration
Very Large Scale Integration
Variable Large Scale Integration
Identify the logic family that combines NMOS and PMOS transistors.
BiCMOS
CMOS
PMOS
TTL
Arsenic and Boron are doped(added) into pure Si to change its ________________
Physical Property
Dimensions
Electrical property
Valence Electrons
Boron having 3 valence electrons creats P type Semiconductor by _____________ Electrons
Donating
Passing
None of the above
Arsenic having 5 valence electrons creats N type Semiconductor by _____________ Electrons
Accepting
Passing
Donating
None of the above
MOS transistor structure is ____________
symmetrical
non symmetrical
semi symmetrical
pseudo symmetrical
Choose the correct ratio for pull-up to pull-down in a CMOS inverter to achieve equal rise and fall times.
1:1
2:1
1:2
3:1
In CMOS logic circuit the p-MOS transistor acts as:
Pull down network
Pull down network
Pull up network
Load
Short to ground
In a CMOS logic circuit, the n-MOS transistor acts as:
Pull down the network
Pull down network
Pull up network
Load
Short to ground
Doubling the amount of transistors in every 18 months, is known as
Gordan's Law
Moore's Law
Moor's law
None of these
A circuit that has 10k~1Billion transistor on chip and is still growing is termed as
MSI
SSI
VLSI
LSI
Miniaturization lead to
Lower Power Consumption
Cheaper Production
Faster Performance
All of the above
None of the above
Key factors demonstrating Moore's Law are:
Clock frequency
Transistor Density
Processor Performance
Power Efficiency
All of the above
Modern processors use transistors with feature sizes below ________ nanometers
5
3
100
1000
Terminals of CMOS
Emitter, Base and Collector
Gate, Source and Drain
NPN and PNP
nMOS and pMOS
MOS is a ___________ device
Voltage and Current Controlled
Current Controlled
Voltage Controlled
Current and Voltage Controlled
PMOS passes ________ and NMOS passes __________
Good 0 Good 0
Good 0, Good 1
Good 1, Good 0
Good 1, Good 1
Pull Up Network(PUN) is constructed using _________
NMOS
PMOS
Both a and b
none
Pull Down Network(PDN) is constructed using _________
NMOS
PMOS
Both a and b
none
CMOS network is constructed using _________
NMOS
PMOS
Both a and b
none
