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WorksheetsQuiz: Logic Gates
Total questions: 50
Worksheet time: 25mins
A logic circuit outputs HIGH only when all three inputs A, B, and C are HIGH. Which gate combination can achieve this if only NAND gates are available?
One NAND gate
Two NAND gates in cascade
Three NAND gates with feedback
Four NAND gates configured as AND equivalent
Which Boolean expression represents a circuit that activates a relay only when at least two of three sensors (A, B, C) are ON?
AB+BC+ACAB + BC + ACAB+BC+AC
A+B+CA + B + CA+B+C
ABACABAC
A'B'+BC'+A'C'A'B' + BC' + A'C'A'B'+BC'+A'C'
If a NOR gate’s inputs are both tied together and connected to signal A, what is the resulting output function?
A
A’
0
1
A system alarm turns ON (logic 1) if the temperature sensor is active (T=1) and either smoke (S=1) or motion (M=1) is detected. What is the Boolean expression?
T(S+M)T(S + M)T(S+M)
T+SMT + SMT+SM
(T+S)M(T + S)M(T+S)M
TS+MTS + MTS+M
Simplify the Boolean expression Y=A'B+AB'/+ABY = A'B + AB' + ABY=A'B+AB'+AB.
A+BA + BA+B
A⊕BA \oplus BA⊕B
A+B'A' + B'A+B'
A+B'+ABA + B' + ABA+B'+AB
Which logic gate’s output is LOW only when all inputs are HIGH?
A. AND
B. OR
C. NAND
D. NOR
In a 4-input AND gate, what is the probability of getting a HIGH output if each input has a 0.5 probability of being HIGH?
0.5
0.0625
0.25
0.125
A fault causes the output of an XOR gate to behave like an OR gate. Which type of failure most likely occurred?
Input shorted to ground
Output stuck-at-1 fault
Missing inverter at output
Cross-connection between inputs
A combinational circuit is defined as Y=(A+B’)(C+D). For A=0,B=1,C=1,D=0, what is Y?
0
1
Undefined
Oscillating
If the Boolean function F(A,B,C)=Σ(1,3,5,7), what simplified expression does it represent?
A. A'+CA' + CA'+C
B. B+CB + CB+C
C. A+BA + BA+B
D. B⊕CB ⊕plus CB⊕C
You must design a logic system that outputs 1 when the number of 1’s in the 3-bit input (A, B, C) is odd. What type of circuit is this?
Parity generator
Comparator
Encoder
Decoder
In a ladder logic representation of an AND gate, both switches must be:
In parallel and closed
In series and closed
In parallel and open
In series and open
Which logic function cannot be realized using only XOR gates?
Odd-parity detection
Even-parity detection
Complement function
Two-input comparison
What is the canonical form of F=A+BCF = A + BCF=A+BC?
A. A+B+CA + B + CA+B+C
B. A+BC+A'B'C'/A + BC + A'B'C'+ABC+A'B'C'
C. AB+AC+BCAB + AC + BCAB+AC+BC
D. AB'C'+A'BC+ABCABC' + A'BC + ABCAB'C'+A'BC+ABC
A system’s output is 1 only when exactly two out of three inputs are 1. What is the Boolean function?
AB+BC+ACAB + BC + ACAB+BC+AC
AB'C'+A'BC'+A'B'CABC' + A'BC' + A'B'CABC'+A'BC'+A'B'C
AB'C+ABC+ABC'ABC' + ABC + ABC'ABC'+A'BC+ABC'
A'B'C'+ABCA'BC' + ABCA'B'C'+ABC
Which logic gate is functionally complete on its own?
XOR
NAND
AND
OR
If a NAND gate has one input permanently tied HIGH, it behaves like:
NOT gate
OR gate
XOR gate
NOR gate
Simplify (A+B)(A+B')(A + B)(A + B')(A+B)(A+B').
A
B
A + B
AB
A 3-input NOR gate output is 1 only when:
All inputs are 1
At least one input is 1
All inputs are 0
Any two inputs are 1
What are the prime numbers between 1 and 10?
6
5
3
2
4
A logic gate has the Boolean expression F=(A+B)'C+AF = (A + B)C + AF=(A+B)'C+A. Simplify it.
A. A+BC/A' + BC'A+BC'
B. A+CA + CA+C
C. AC+A'B/AC + A'B'AC+A'B'
D. A+B'CA + B'CA+BC
In a relay logic system, a parallel contact arrangement corresponds to which digital logic gate?
AND
OR
NOR
NAND
Which of the following circuits implements the function Y=AB+A'C'?
Comparator (A = B)
XOR gate
NOR-AND combination
Half-subtractor
In a fault-tolerant design, a triple modular redundancy (TMR) circuit uses:
2 majority gates and 1 inverter
3 identical logic modules with majority voting
3 inverters in parallel
2 parity checkers and 1 latch
Simplify the Boolean function Y=A'B'C+A'BC+AB'CY = A'BC + A'BC + AB'CY=A'B'C+A'BC+ABC.
C(A'+B')C(A' + B')C(A'+B')
C(A'+B)C(A' + B)C(A'+B)
C(A'+AB)C(A' + AB)C(A'+AB)
C(B+A')C(B + A')C(B+A')
A logic analyzer shows a 4-bit signal cycling through 0000 → 0001 → 0011 → 0111 → 1111 and repeats. Which circuit most likely produces this pattern?
Binary up-counter
Ring counter
Johnson counter
Asynchronous ripple adder
You are tasked to design a car door safety system where the alarm turns ON if door is open (D = 1) AND ignition is ON (I = 1). Which expression represents the logic?
D+ID + ID+I
D'I'D'I'D'I'
DIDIDI
D+I'D + I'D+I'
A three-input logic gate produces an output 1 only when exactly two inputs are high. What type of gate behavior does this describe?
A. XOR
B. XNOR
C. Majority logic gate
D. Parity checker
You observe that a NAND gate connected to another NAND gate behaves as an AND gate. This happens because:
The output of the first gate inverts the input of the second
NAND is the complement of OR
Two-level NAND configuration eliminates inversion
The input-output inversion cancels out
A logic circuit controlling an automatic streetlight turns ON when it is dark (L = 0) and motion is detected (M = 1). Which simplified Boolean expression matches this?
L'ML'M'L'M
LM'L'M'L'M'
L'+ML' + M'L+M'
L'+ML' + ML'+M
If a half-adder circuit has inputs A = 1 and B = 1, what will be the Sum and Carry outputs?
Sum = 1, Carry = 1
Sum = 0, Carry = 1
Sum = 1, Carry = 0
Sum = 0, Carry = 0
In a BCD-to-7-segment display, segment “g” lights for certain binary inputs. What logic function is being implemented in that segment driver?
Combinational logic
Sequential logic
Latch logic
Analog logic
A logic gate is used to debounce a mechanical switch. Which gate type helps achieve this when paired with a capacitor?
XOR
AND
Schmitt Trigger
OR
A circuit outputs 1 only if A and B are not equal. Identify the logic gate.
XNOR
XOR
NAND
In an elevator safety system, the control signal activates only if weight < limit AND door closed AND floor selected. This logic function can be implemented using:
Multi-input AND gate
XOR gate
3-to-8 Decoder
Full Adder
A combinational circuit outputs 1 for binary inputs 010 and 101. What is the Boolean expression in SOP form?
A. A'B'C+ABC'A'BC + ABC'A'B'C+ABC'
B. A'BC+ABC'A'BC' + ABC'A'BC'+ABC'
C. A'BC+ABC'A'BC + ABC'A'BC+ABC'
D. A'BC+ABC'A'BC + ABC'A'B'C+ABC'
If a logic circuit uses a universal gate to perform any logic function, which gate could that be?
AND
OR
NAND
XOR
A sensor-based security system has three sensors: Door (D), Window (W), and Motion (M). The alarm triggers when any two or more sensors are active. Which Boolean function best represents this?
DW'+DM'+WDMW + DM + WMDW+DM+WM
D+W+MD + W + MD+W+M
DWM'+DWM+DW'MDWM' + DWM + DW'MDWM'+D'WM+DW'M
DW'M'+D'WM+DW'MDWM' + D'WM + DW'MDW'M'+D'WM+DW'M
NOR
NOR
XOR
AND
NOR
A designer uses De Morgan’s theorem to simplify the expression (AB)’+C(AB)’ + C(AB)’+C. What is the equivalent?
A. A’+B’+CA’ + B’ + CA’+B’+C
B. (A+B)’+C(A + B)’ + C(A+B)’+C
C. A’B’+CA’B’ + CA’B’+C
D. (A’+B’)C(A’ + B’)C(A’+B’)C’
An industrial control panel outputs HIGH when machine is ON and temperature < 80°C. If M=1 (ON), T=0 (below limit), what logic operation is needed?
M+TM’ + TM’+T’
MT’MT’MT
M’T’MT’MT
M’+TM’ + TM’+T
A NAND–NOR combination produces an inverted output of an AND gate. Which Boolean property supports this behavior?
Duality
Distributive
Complementation
Absorption
You need to detect if a binary number is divisible by 2. Which single input should be analyzed in the logic circuit?
Most significant bit
Least significant bit
Carry input
When the input to a NOT gate changes from LOW to HIGH, the output experiences a propagation delay. Which factor most affects this?
Gate capacitance
Power supply voltage
Ambient temperature
Input current
A designer replaces all AND–OR combinations with NAND-only logic to simplify fabrication. This principle is known as:
Functional completeness
Logic synthesis
Canonical conversion
Threshold logic
A 4-to-1 MUX is used to implement a logic function F(A,B,C)=Σ(1,2,6,7). Which inputs of the MUX should be tied HIGH?
D. D1, D2, D6, D7
B. D0, D3, D4, D5
C. D1, D2, D4, D7
A. D1, D2, D6, D7
In relay control logic, an inverter output drives a transistor switch. What is the main reason for this design?
To ensure fail-safe OFF condition
To reduce current draw
To increase response time
To minimize input noise
A logic gate array is used to implement programmable control for an elevator. Which technology allows modification of gate connections post-fabrication?
FPGA
TTL
CMOS
PLA (fixed)
A traffic light controller cycles through RED, GREEN, and YELLOW states using flip-flops. The control logic type is:
Combinational
Sequential
Hybrid
Recursive
An electrical engineering student measures an unexpected oscillation at the output of a NOT gate. The most probable cause is:
Noise coupling or feedback loop
Incorrect truth table implementation
Power supply overvoltage
Missing pull-up resistor
