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Quiz: Logic Gates

Total questions: 50

Worksheet time: 25mins

Name
Class
Date
1.

A logic circuit outputs HIGH only when all three inputs A, B, and C are HIGH. Which gate combination can achieve this if only NAND gates are available?

a)

One NAND gate

b)

Two NAND gates in cascade

c)

Three NAND gates with feedback

d)

Four NAND gates configured as AND equivalent

2.

Which Boolean expression represents a circuit that activates a relay only when at least two of three sensors (A, B, C) are ON?

a)

AB+BC+ACAB + BC + ACAB+BC+AC

b)

A+B+CA + B + CA+B+C

c)

ABACABAC

d)

A'B'+BC'+A'C'A'B' + BC' + A'C'A'B'+BC'+A'C'

3.

If a NOR gate’s inputs are both tied together and connected to signal A, what is the resulting output function?

a)

A

b)

A’

c)

0

d)

1

4.

A system alarm turns ON (logic 1) if the temperature sensor is active (T=1) and either smoke (S=1) or motion (M=1) is detected. What is the Boolean expression?

a)

T(S+M)T(S + M)T(S+M)

b)

T+SMT + SMT+SM

c)

(T+S)M(T + S)M(T+S)M

d)

TS+MTS + MTS+M

5.

Simplify the Boolean expression Y=A'B+AB'/+ABY = A'B + AB' + ABY=A'B+AB'+AB.

a)

A+BA + BA+B

b)

A⊕BA \oplus BA⊕B

c)

A+B'A' + B'A+B'

d)

A+B'+ABA + B' + ABA+B'+AB

6.

Which logic gate’s output is LOW only when all inputs are HIGH?

a)

A. AND

b)

B. OR

c)

C. NAND

d)

D. NOR

7.

In a 4-input AND gate, what is the probability of getting a HIGH output if each input has a 0.5 probability of being HIGH?

a)

0.5

b)

0.0625

c)

0.25

d)

0.125

8.

A fault causes the output of an XOR gate to behave like an OR gate. Which type of failure most likely occurred?

a)

Input shorted to ground

b)

Output stuck-at-1 fault

c)

Missing inverter at output

d)

Cross-connection between inputs

9.

A combinational circuit is defined as Y=(A+B’)(C+D). For A=0,B=1,C=1,D=0, what is Y?

a)

0

b)

1

c)

Undefined

d)

Oscillating

10.

If the Boolean function F(A,B,C)=Σ(1,3,5,7), what simplified expression does it represent?

a)

A. A'+CA' + CA'+C

b)

B. B+CB + CB+C

c)

C. A+BA + BA+B

d)

D. B⊕CB ⊕plus CB⊕C

11.

You must design a logic system that outputs 1 when the number of 1’s in the 3-bit input (A, B, C) is odd. What type of circuit is this?

a)

Parity generator

b)

Comparator

c)

Encoder

d)

Decoder

12.

In a ladder logic representation of an AND gate, both switches must be:

a)

In parallel and closed

b)

In series and closed

c)

In parallel and open

d)

In series and open

13.

Which logic function cannot be realized using only XOR gates?

a)

Odd-parity detection

b)

Even-parity detection

c)

Complement function

d)

Two-input comparison

14.

What is the canonical form of F=A+BCF = A + BCF=A+BC?

a)

A. A+B+CA + B + CA+B+C

b)

B. A+BC+A'B'C'/A + BC + A'B'C'+ABC+A'B'C'

c)

C. AB+AC+BCAB + AC + BCAB+AC+BC

d)

D. AB'C'+A'BC+ABCABC' + A'BC + ABCAB'C'+A'BC+ABC

15.

A system’s output is 1 only when exactly two out of three inputs are 1. What is the Boolean function?

a)

AB+BC+ACAB + BC + ACAB+BC+AC

b)

AB'C'+A'BC'+A'B'CABC' + A'BC' + A'B'CABC'+A'BC'+A'B'C

c)

AB'C+ABC+ABC'ABC' + ABC + ABC'ABC'+A'BC+ABC'

d)

A'B'C'+ABCA'BC' + ABCA'B'C'+ABC

16.

Which logic gate is functionally complete on its own?

a)

XOR

b)

NAND

c)

AND

d)

OR

17.

If a NAND gate has one input permanently tied HIGH, it behaves like:

a)

NOT gate

b)

OR gate

c)

XOR gate

d)

NOR gate

18.

Simplify (A+B)(A+B')(A + B)(A + B')(A+B)(A+B').

a)

A

b)

B

c)

A + B

d)

AB

19.

A 3-input NOR gate output is 1 only when:

a)

All inputs are 1

b)

At least one input is 1

c)

All inputs are 0

d)

Any two inputs are 1

20.

What are the prime numbers between 1 and 10?

a)

6

b)

5

c)

3

d)

2

e)

4

21.

A logic gate has the Boolean expression F=(A+B)'C+AF = (A + B)C + AF=(A+B)'C+A. Simplify it.

a)

A. A+BC/A' + BC'A+BC'

b)

B. A+CA + CA+C

c)

C. AC+A'B/AC + A'B'AC+A'B'

d)

D. A+B'CA + B'CA+BC

22.

In a relay logic system, a parallel contact arrangement corresponds to which digital logic gate?

a)

AND

b)

OR

c)

NOR

d)

NAND

23.

Which of the following circuits implements the function Y=AB+A'C'?

a)

Comparator (A = B)

b)

XOR gate

c)

NOR-AND combination

d)

Half-subtractor

24.

In a fault-tolerant design, a triple modular redundancy (TMR) circuit uses:

a)

2 majority gates and 1 inverter

b)

3 identical logic modules with majority voting

c)

3 inverters in parallel

d)

2 parity checkers and 1 latch

25.

Simplify the Boolean function Y=A'B'C+A'BC+AB'CY = A'BC + A'BC + AB'CY=A'B'C+A'BC+ABC.

a)

C(A'+B')C(A' + B')C(A'+B')

b)

C(A'+B)C(A' + B)C(A'+B)

c)

C(A'+AB)C(A' + AB)C(A'+AB)

d)

C(B+A')C(B + A')C(B+A')

26.

A logic analyzer shows a 4-bit signal cycling through 0000 → 0001 → 0011 → 0111 → 1111 and repeats. Which circuit most likely produces this pattern?

a)

Binary up-counter

b)

Ring counter

c)

Johnson counter

d)

Asynchronous ripple adder

27.

You are tasked to design a car door safety system where the alarm turns ON if door is open (D = 1) AND ignition is ON (I = 1). Which expression represents the logic?

a)

D+ID + ID+I

b)

D'I'D'I'D'I'

c)

DIDIDI

d)

D+I'D + I'D+I'

28.

A three-input logic gate produces an output 1 only when exactly two inputs are high. What type of gate behavior does this describe?

a)

A. XOR

b)

B. XNOR

c)

C. Majority logic gate

d)

D. Parity checker

29.

You observe that a NAND gate connected to another NAND gate behaves as an AND gate. This happens because:

a)

The output of the first gate inverts the input of the second

b)

NAND is the complement of OR

c)

Two-level NAND configuration eliminates inversion

d)

The input-output inversion cancels out

30.

A logic circuit controlling an automatic streetlight turns ON when it is dark (L = 0) and motion is detected (M = 1). Which simplified Boolean expression matches this?

a)

L'ML'M'L'M

b)

LM'L'M'L'M'

c)

L'+ML' + M'L+M'

d)

L'+ML' + ML'+M

31.

If a half-adder circuit has inputs A = 1 and B = 1, what will be the Sum and Carry outputs?

a)

Sum = 1, Carry = 1

b)

Sum = 0, Carry = 1

c)

Sum = 1, Carry = 0

d)

Sum = 0, Carry = 0

32.

In a BCD-to-7-segment display, segment “g” lights for certain binary inputs. What logic function is being implemented in that segment driver?

a)

Combinational logic

b)

Sequential logic

c)

Latch logic

d)

Analog logic

33.

A logic gate is used to debounce a mechanical switch. Which gate type helps achieve this when paired with a capacitor?

a)

XOR

b)

AND

c)

Schmitt Trigger

d)

OR

34.

A circuit outputs 1 only if A and B are not equal. Identify the logic gate.

a)

XNOR

b)

XOR

c)

NAND

35.

In an elevator safety system, the control signal activates only if weight < limit AND door closed AND floor selected. This logic function can be implemented using:

a)

Multi-input AND gate

b)

XOR gate

c)

3-to-8 Decoder

d)

Full Adder

36.

A combinational circuit outputs 1 for binary inputs 010 and 101. What is the Boolean expression in SOP form?

a)

A. A'B'C+ABC'A'BC + ABC'A'B'C+ABC'

b)

B. A'BC+ABC'A'BC' + ABC'A'BC'+ABC'

c)

C. A'BC+ABC'A'BC + ABC'A'BC+ABC'

d)

D. A'BC+ABC'A'BC + ABC'A'B'C+ABC'

37.

If a logic circuit uses a universal gate to perform any logic function, which gate could that be?

a)

AND

b)

OR

c)

NAND

d)

XOR

38.

A sensor-based security system has three sensors: Door (D), Window (W), and Motion (M). The alarm triggers when any two or more sensors are active. Which Boolean function best represents this?

a)

DW'+DM'+WDMW + DM + WMDW+DM+WM

b)

D+W+MD + W + MD+W+M

c)

DWM'+DWM+DW'MDWM' + DWM + DW'MDWM'+D'WM+DW'M

d)

DW'M'+D'WM+DW'MDWM' + D'WM + DW'MDW'M'+D'WM+DW'M

39.

NOR

a)

NOR

b)

XOR

c)

AND

d)

NOR

40.

A designer uses De Morgan’s theorem to simplify the expression (AB)’+C(AB)’ + C(AB)’+C. What is the equivalent?

a)

A. A’+B’+CA’ + B’ + CA’+B’+C

b)

B. (A+B)’+C(A + B)’ + C(A+B)’+C

c)

C. A’B’+CA’B’ + CA’B’+C

d)

D. (A’+B’)C(A’ + B’)C(A’+B’)C’

41.

An industrial control panel outputs HIGH when machine is ON and temperature < 80°C. If M=1 (ON), T=0 (below limit), what logic operation is needed?

a)

M+TM’ + TM’+T’

b)

MT’MT’MT

c)

M’T’MT’MT

d)

M’+TM’ + TM’+T

42.

A NAND–NOR combination produces an inverted output of an AND gate. Which Boolean property supports this behavior?

a)

Duality

b)

Distributive

c)

Complementation

d)

Absorption

43.

You need to detect if a binary number is divisible by 2. Which single input should be analyzed in the logic circuit?

a)

Most significant bit

b)

Least significant bit

c)

Carry input

44.

When the input to a NOT gate changes from LOW to HIGH, the output experiences a propagation delay. Which factor most affects this?

a)

Gate capacitance

b)

Power supply voltage

c)

Ambient temperature

d)

Input current

45.

A designer replaces all AND–OR combinations with NAND-only logic to simplify fabrication. This principle is known as:

a)

Functional completeness

b)

Logic synthesis

c)

Canonical conversion

d)

Threshold logic

46.

A 4-to-1 MUX is used to implement a logic function F(A,B,C)=Σ(1,2,6,7). Which inputs of the MUX should be tied HIGH?

a)

D. D1, D2, D6, D7

b)

B. D0, D3, D4, D5

c)

C. D1, D2, D4, D7

d)

A. D1, D2, D6, D7

47.

In relay control logic, an inverter output drives a transistor switch. What is the main reason for this design?

a)

To ensure fail-safe OFF condition

b)

To reduce current draw

c)

To increase response time

d)

To minimize input noise

48.

A logic gate array is used to implement programmable control for an elevator. Which technology allows modification of gate connections post-fabrication?

a)

FPGA

b)

TTL

c)

CMOS

d)

PLA (fixed)

49.

A traffic light controller cycles through RED, GREEN, and YELLOW states using flip-flops. The control logic type is:

a)

Combinational

b)

Sequential

c)

Hybrid

d)

Recursive

50.

An electrical engineering student measures an unexpected oscillation at the output of a NOT gate. The most probable cause is:

a)

Noise coupling or feedback loop

b)

Incorrect truth table implementation

c)

Power supply overvoltage

d)

Missing pull-up resistor