WorksheetsIHDL_FinalsDF
Total questions: 20
Worksheet time: 10mins
Which Verilog keyword is used in dataflow modeling?
always
assign
case
initial
Dataflow modeling mainly describes circuits using:
Logic gates
Boolean equations
Memory elements
Flip-flops
What type of circuit is best modeled with dataflow style?
Sequential circuits
Mixed-signal circuits
Combinational circuits
Microprocessors
What does this line represent? assign Y = A | B;
Behavioral modeling
Gate-level modeling
Dataflow modeling
Sequential modeling
The conditional operator ?: is used in dataflow modeling to implement:
Flip-flops
Multiplexers
Counters
Registers
Which operator performs bit-by-bit OR?
||
|
&
==
The expression assign S = A ^ B; implements:
AND gate
OR gate
XOR gate
NAND gate
What is the output width of the expression A & B when A and B are 4 bits?
1 bit
2 bits
4 bits
8 bits
Which operator reduces all bits of a vector to 1 value?
&&
|
^
& (reduction)
The expression assign Y = &A; means:
bitwise AND
logical AND
reduction AND
case statement
What is the result of assign Y = A && B; when A = 4'b0001 and B = 4'b1111?
4'b0001
4'b1111
1
0
The conditional operator syntax is:
condition ? value1 : value2
if (condition) value1 else value2
condition -> value1 | value2
(condition || value1) && value2
The following code implements a: assign Y = (A > B);
Decoder
Comparator
Mux
Gate
Which of the following is TRUE for dataflow modeling?
Uses procedural blocks
Uses continuous assignment
Best for sequential logic
Requires clock signals
What will this expression output when A = 3'b101? assign P = ^A;
1
0
3
101
Which operator performs logical OR?
|
||
&
^
What is the function of assign in Verilog?
Defines a procedural block
Declares a memory cell
Continuously drives a signal
Creates hardware registers
What circuit does this represent? assign Y = (S == 0) ? A : B;
Encoder
Decoder
Multiplexer
Comparator
For vector A = 4’b1101, what is |A (reduction OR)?
0
1
1101
1111
The main advantage of dataflow modeling is:
Describes circuits at gate level
Allows complex algorithmic descriptions
Very readable for combinational expressions
Requires clocking
