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WorksheetsThe Fallingwater Analogy
Total questions: 62
Worksheet time: 31mins
Which idea best captures principled design when using the Fallingwater analogy in IT systems?
Changing goals repeatedly during implementation
Adhering to core design principles consistently
Prioritizing aesthetics over system reliability
Maximizing features regardless of constraints
In architecture and computing, organic architecture suggests what design approach?
Using rigid modular rules without exceptions
Separating components to avoid interactions
Focusing only on performance benchmarks
Integrating system with its environment harmoniously
A design tradeoff highlighted by the Fallingwater analogy would most likely involve which choice?
Ignoring site conditions to simplify construction
Avoiding any compromises to meet perfection
Selecting every possible feature without limits
Balancing aesthetic integration with structural constraints
You must propose a system architecture for a workload with frequent memory row conflicts. Which principle-guided strategy aligns with the analogy?
Delay decisions until hardware issues disappear
Choose an ISA and microarchitecture that mitigate contention
Add more unrelated features to impress stakeholders
Rely solely on compiler optimizations for fixes
When applying creative thinking to IT design inspired by Fallingwater, what is a practical step?
Generate solutions that fit constraints and context
Ignore limitations to brainstorm without boundaries
Copy existing designs without adaptation
Focus on one metric and disregard others
Which statement best distinguishes design principles from design precedents in IT systems?
Principles are opinions of designers; precedents are regulations
Principles are universal rationales; precedents are past solutions
Principles are vendor practices; precedents are scientific laws
Principles are old examples; precedents are timeless theories
A team faces cache interference across cores. Which approach reflects out-of-the-box thinking grounded in principles rather than copying precedents?
Replicate another vendor’s cache hierarchy exactly
Analyze memory contention at each layer, redesign controller policy
Adopt the most cited scheduling algorithm unchanged
Increase DRAM capacity following typical upgrades
Breaking abstraction layers can help solve performance issues. Which action applies this concept to the DRAM interface shown?
Rely solely on operating system defaults for memory
Only optimize application code without hardware insight
Ignore lower-level behavior and add more cores
Profile access patterns, tune controller-to-bank mapping
Which component pair forms the fundamental elements of a DRAM cell, as shown in the diagram?
Two capacitors in parallel
A capacitor and access transistor
Two access transistors in series
A flip-flop and buffer gate
Why must each DRAM row be periodically refreshed?
To rebalance load across ranks
Capacitor charge leaks over time
Wordlines drift due to thermal noise
To rewrite corrupted parity bits
A system has 1 Exabyte of DRAM with 8 KB rows. Approximately how many rows does it contain?
About 1.34e11 rows
About 1.25e16 rows
About 1.34e14 rows
About 1.25e8 rows
Which downside directly affects performance predictability during DRAM refresh?
Energy per refresh increases heat
Ranks unavailable cause pause times
Higher leakage reduces retention time
Refresh limits capacity scaling
Which statement best captures the multi-directional focus of a computer architect?
Looking backward, forward, up, and down across computing
Looking only forward to future device technologies
Looking upward at applications and software stacks
Looking downward to circuits and manufacturing details
In the computing stack, which pair correctly represents looking up and looking down for a computer architect?
Up: DRAM cells; Down: operating systems
Up: circuits; Down: compilers
Up: instruction set; Down: user requirements
Up: applications; Down: device technology
From the performance chart, what trend is shown as DRAM device capacity increases?
Higher percentage of time spent refreshing
Refresh time peaks at mid-range capacity only
Lower percentage of time spent refreshing
Unchanged refresh time percentage across capacities
Which rationale explains why refresh overhead becomes a design tradeoff for future DRAM systems?
Refresh reduces error rates as capacity increases
Refresh overhead is dominated by CPU arithmetic operations
Refresh consumes more performance and energy at larger capacities
Refresh becomes unnecessary due to perfect retention
What question on the problem-solving slide encourages architectural innovation about DRAM refresh?
Must buses always be synchronous for reliability?
Is virtual memory needed for embedded systems?
Do we need to refresh all rows every 64ms?
Should caches be write-through at all levels?
Which strategy aligns with exposing lower-level information to upper layers to reduce refresh overhead?
Retention-aware refresh using device-level knowledge
Uniform periodic refresh regardless of cell behavior
Increasing CPU frequency to mask memory stalls
Ignoring device variability to simplify controllers
From the energy chart, what approximate fraction of DRAM energy may be spent on refresh at 64 Gb capacity?
About fifteen percent of total DRAM energy
About eight percent of total DRAM energy
About forty-seven percent of total DRAM energy
About twenty-six percent of total DRAM energy
Which duty best represents "looking backward" in an architect’s role?
Mapping APIs to hardware features
Forecasting emerging workload trends
Selecting future fabrication processes
Analyzing historical design trade-offs
What does "looking forward" primarily require from a systems architect?
Minimizing compiler optimization barriers
Auditing current operational incidents
Documenting past performance regressions
Predicting technology and workload evolution
In "looking up/down," what interface is most central to bridge effectively?
Physical data center cooling methods
Hardware/software boundary and contracts
User interface accessibility guidelines
Network transport layer protocols
Which set best captures system design goals an architect balances?
Aesthetics, branding, licensing, layout
Monetization, advertising, virality, reach
Performance, efficiency, reliability, cost
Gamification, badges, leaderboards, scores
When deciding how much low-level profile information to expose, what trade-offs arise?
Marketing, hiring, training, travel
Logging, alerting, paging, reporting
Overhead, power, verification, cost
Caching, paging, swapping, hashing
To whom might retention-time profile information be exposed for best system impact?
DFS, CDN, SEO, CRM subsystems
Memory controller, OS, programmer, compiler
Printers, scanners, cameras, displays
End users, sales team, HR, finance
Which reasoning best justifies parallelizing DRAM refreshes with accesses?
Serialize accesses to ensure strict consistency
Disable refresh to save dynamic power always
Overlap refresh latency to improve throughput
Increase refresh duration to reduce wear-out
Which statement best describes the role of abstraction layers in computing systems?
They hide low-level details to manage complexity
They eliminate hardware to simplify programming
They guarantee performance regardless of workload
They convert analog signals into digital signals
In the hierarchy from problems to electrons, where does the Instruction Set Architecture (ISA) primarily operate?
Inside the compiler optimization stage
Between software and microarchitecture boundary
Above high-level application requirements
Below transistor fabrication processes
What is microarchitecture responsible for relative to the ISA?
Regulating power by operating system policies
Implementing ISA operations using hardware structures
Defining the programmer-visible instruction formats
Translating high-level languages into machine code
Which action exemplifies breaking abstraction layers to design better systems?
Relying solely on compiler defaults for performance
Using hardware retention profiling to tune refresh rates
Writing code only against standard library interfaces
Ignoring cache behavior to keep code portable
RAIDR’s key idea for DRAM refresh can be summarized as what policy?
Refresh weak rows more often, strong rows less often
Refresh all rows uniformly at the shortest interval
Duplicate rows to avoid retention-time profiling
Disable refresh to reduce dynamic power usage
Which step in RAIDR stores rows by retention time using compact metadata?
Binning with Bloom Filters in the controller
Profiling with operating system timers
Encoding with error-correcting codes
Refreshing with fixed auto-refresh commands
What phenomenon is illustrated when repeatedly activating a DRAM aggressor row causes bit flips in neighbors?
Instruction-level hazards in pipelines
Disturbance errors in adjacent victim rows
Write-back stalls in cache hierarchy
Voltage droop in power delivery network
Why can cooperation across components and layers yield more effective systems?
Cross-layer information enables targeted optimizations
More layers guarantee fewer bugs by design
Adding interfaces always reduces energy consumption
Ignoring lower levels avoids complexity in solutions
Which concept best distinguishes productivity from efficiency in IT system design?
Maximizing output per unit resource consumed
Doing more tasks regardless of resource cost
Using the newest hardware without optimization
Adding more software layers for modularity
Why is crossing abstraction layers important when dealing with DRAM disturbance errors shown across CPU architectures?
It enables coordinated fixes across hardware and software
It simplifies documentation for developers
It removes the need for error monitoring
It guarantees zero errors on all platforms
Which action is an example of tolerating memory disturbance errors at the hardware/software interface?
Throttle CPUs to reduce access rates only
Ignore errors and rely on user reports
Use stronger error correcting codes proactively
Replace DRAM with a different technology
Given the access rates and error counts, which inference supports a performance–reliability trade-off across architectures?
Access rate is irrelevant to reliability planning
Higher access rates always eliminate errors
Errors are independent of access behavior
Lower error counts can occur at moderate access rates
Which approach best embodies embracing heterogeneity across abstraction layers to manage disturbance errors?
Disable caching to force uniform memory reliability
Standardize all modules to identical reliability levels
Move all computation to external storage devices
Map error-tolerant data to less reliable memory sections
In a multi-core processor, which shared resource is most likely to cause system-wide slowdowns when one thread becomes a memory performance hog?
Dedicated integer ALUs
Per-core branch predictors
Shared last-level cache bandwidth
Private L1 instruction caches
Which scenario best illustrates resource contention in a multi-core system leading to unexpected performance drops?
One core streaming large arrays saturating memory bandwidth
Each core running short control-heavy tasks
Two cores executing independent integer arithmetic
Cores idling while waiting for IO interrupts
What is the primary effect when interconnect contention rises due to a memory-intensive workload on one core?
Reduced branch prediction accuracy across cores
Improved locality in private L1 caches
Increased latency for cache-to-memory transactions
Higher throughput of floating-point pipelines
A four-core system has a shared last-level cache and a ring interconnect. One core runs a bandwidth-heavy copy loop. Which mitigation is most likely to reduce cross-core slowdowns without changing the algorithm?
Pin the copy loop to a core closer to memory controller
Disable private L1 caches on all cores
Increase integer ALU issue width per core
Lower the branch predictor table size
When a single thread becomes a memory performance hog, which symptom would you expect in the other cores’ memory access profiles?
More stalled cycles waiting on interconnect
Faster commit rates in integer pipelines
Shorter average memory access times
Lower miss rates at all cache levels
Which design choice can help isolate heavy memory traffic and reduce shared resource contention in multi-core systems?
Unified execution pipeline shared across threads
Global branch predictor shared by all cores
Per-core private last-level caches with no sharing
Partitioned or QoS-controlled shared cache and memory bandwidth
In a DRAM bank diagram, which component caches the most recently activated row to serve subsequent accesses quickly?
Row buffer inside bank
Command queue in controller
Column decoder buffer
Global address latch
A memory access that targets the currently open row in a DRAM bank is called what?
Row-conflict access
Row-skip access
Row-hit access
Row-miss access
Which sequence best describes serving a row-conflict in a DRAM bank?
Refresh then issue WRITE
Issue READ immediately
Precharge then activate new row
Activate then precharge row
In FR-FCFS scheduling, which request is prioritized first among ready requests?
Oldest request regardless of type
Row-hit ready request
Highest address request
Writeback cleanup request
What is the main unfairness risk of FR-FCFS scheduling under mixed workloads?
Starves refresh operations entirely
Ignores bank-level parallelism
Prefers writes over reads always
Keeps row-hit stream dominating others
Which action closes the currently open row in a DRAM bank to prepare for activating another row?
Precharge command
Burst terminate
Activate command
Refresh command
When multiple banks exist, which policy increases throughput by exploiting parallelism while minimizing conflicts?
Round-robin per core
Bank-aware FR-FCFS
Close-page on every access
Always-open row policy
Which timing constraint limits how quickly a controller can issue an ACT to a different row in the same bank after a PRE?
tRCD constraint
tRAS constraint
tWR constraint
tRP constraint
A controller that batches writes to drain the write queue primarily aims to reduce which cost?
Row activation energy
Read-to-write turnaround
Address bus contention
Bank refresh overhead
Which memory access pattern typically maximizes row buffer locality in DRAM and thus improves throughput under common scheduling policies?
Uniformly distributed accesses with large strides
Interleaved accesses alternating rows per request
Streamed accesses within the same open row
Random accesses across many banks and rows
Bursty accesses with irregular stride
In a memory performance attack, which condition most directly leads to denial of service for a victim application?
Victim has low cache hit rate only
Attacker monopolizes row buffer hits
Controller disables refresh operations
Victim uses multiple memory channels
Attacker reduces precharge timing
Why can random access patterns exploit unfairness in certain DRAM controllers?
They make refresh invisible to scheduling
They increase page hits for all threads
They reduce command bus utilization
They force frequent precharges and row conflicts
They avoid bank-level parallelism entirely
Which factor best defines memory intensity when analyzing susceptibility to performance attacks?
Depth of the reorder buffer
Proportion of time stalled on memory
Number of cores in the processor
Frequency of branch mispredictions
Size of the instruction cache only
A DRAM controller favoring row-buffer hits with FR-FCFS scheduling is most likely to:
Prioritize random requests with long latency
Throttle all threads equally under load
Close the row after every single access
Prioritize requests that hit the open row
Prioritize oldest requests regardless of row state
An attacker issues a stream of accesses to one hot row while a victim issues random accesses. What is the expected outcome?
Controller grants attacker priority causing victim slowdowns
Attacker suffers more precharges than the victim
Victim experiences more row hits and higher throughput
Both threads get equal service due to fairness
Row buffer thrashing eliminates any advantage
Which mitigation most directly reduces unfairness caused by row buffer locality exploitation?
Increase DRAM refresh rate significantly
Adopt request prioritization caps per thread
Disable bank interleaving entirely
Use larger last-level caches only
Always close rows immediately after activation
When evaluating a suspected memory denial-of-service scenario, which evidence best supports the diagnosis?
High CPU utilization with few memory stalls
Lower queue occupancy in the controller
Victim’s row-hit rate plummets under attacker load
Reduced bank-level parallelism for the attacker
Stable instruction throughput across all threads
