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UNIT–I: ARM Architecture Quiz

Total questions: 30

Worksheet time: 15mins

Name
Class
Date
1.

ARM design philosophy primarily emphasizes:

a)

High clock frequency over power

b)

Complex instruction execution

c)

Low power consumption and high code density

d)

Superscalar execution

2.

ARM processors follow which architecture?

a)

CISC

b)

RISC

c)

VLIW

d)

EPIC

3.

Which feature contributes most to ARM’s high code density?

a)

Fixed 32-bit instructions

b)

Thumb instruction set

c)

Deep pipelines

d)

Superscalar execution

4.

Which ARM processor family is mainly used in microcontrollers?

a)

ARM9

b)

ARM11

c)

Cortex-A

d)

Cortex-M

5.

Which ARM family is designed for high-performance applications like smartphones?

a)

Cortex-M

b)

Cortex-R

c)

Cortex-A

d)

ARM7

6.

How many general-purpose registers are available in ARM architecture?

a)

8

b)

12

c)

16

d)

32

7.

Which register holds the current program status in ARM?

a)

SPSR

b)

CPSR

c)

PC

d)

LR

8.

CPSR stands for:

a)

Current Processor State Register

b)

Current Program Status Register

c)

Control Program Status Register

d)

Central Program Status Register

9.

Which flag in CPSR indicates a negative result?

a)

Z

b)

C

c)

V

d)

N

10.

Which ARM register stores the return address of a subroutine?

a)

PC

b)

SP

c)

LR

d)

CPSR

11.

ARM pipeline typically consists of how many stages?

a)

2

b)

3

c)

5

d)

7

12.

The three stages of ARM pipeline are:

a)

Fetch, Decode, Execute

b)

Fetch, Issue, Commit

c)

Decode, Execute, Write

d)

Load, Store, Execute

13.

Pipelining mainly improves:

a)

Memory size

b)

Power consumption

c)

Instruction throughput

d)

Instruction size

14.

What happens during an ARM exception?

a)

Program terminates

b)

CPU switches to exception mode

c)

Cache is flushed

d)

Pipeline is disabled permanently

15.

Which exception has the highest priority in ARM?

a)

IRQ

b)

FIQ

c)

Reset

d)

Software interrupt

16.

The ARM vector table contains:

a)

Data addresses

b)

Instruction opcodes

c)

Exception handler addresses

d)

Register values

17.

At which address is the ARM vector table usually located?

a)

0x00000000

b)

0x10000000

c)

0x20000000

d)

0xFFFFFFFF

18.

Which interrupt type is faster in ARM?

a)

IRQ

b)

FIQ

c)

SWI

d)

Abort

19.

Memory hierarchy improves system performance by:

a)

Increasing instruction size

b)

Reducing memory access time

c)

Increasing CPU registers

d)

Reducing clock speed

20.

Which memory is fastest in the ARM memory hierarchy?

a)

Cache

b)

Main memory

c)

Secondary storage

d)

Flash

21.

Cortex-M4 differs from Cortex-M3 by supporting:

a)

Higher clock speed only

b)

Floating-point and DSP instructions

c)

Virtual memory

d)

MMU

22.

Which Cortex-M processor supports DSP extensions?

a)

Cortex-M0

b)

Cortex-M3

c)

Cortex-M4

d)

Cortex-M1

23.

ARM processors are widely used because they offer:

a)

High cost and complexity

b)

Low power and efficiency

c)

Large instruction sets

d)

High heat dissipation

24.

Which register points to the next instruction to be executed?

a)

LR

b)

SP

c)

PC

d)

CPSR

25.

Which ARM exception occurs due to invalid memory access?

a)

IRQ

b)

Reset

c)

Abort

d)

FIQ

26.

ARM architecture supports which instruction execution?

a)

Parallel only

b)

Sequential only

c)

Conditional execution

d)

Random execution

27.

Conditional execution in ARM reduces:

a)

Register usage

b)

Branch instructions

c)

Clock frequency

d)

Memory size

28.

Which component stores frequently accessed data?

a)

Cache

b)

ROM

c)

Flash

d)

Secondary memory

29.

ARM processors are best suited for:

a)

Supercomputers

b)

Embedded systems

c)

Mainframe systems

d)

Desktop CPUs

30.

The main goal of ARM architecture is to achieve:

a)

Maximum speed only

b)

Balanced performance and power efficiency

c)

High instruction complexity

d)

Large silicon area