NEW
Font size
WorksheetsSemiconductor Memories
Total questions: 50
Worksheet time: 2hrs 40mins
Semiconductor memory devices are broadly classified as:
Sequential and combinational memories
Volatile random access memories and nonvolatile memories
Static and dynamic flip-flop memories
Bipolar and MOS memories
In volatile RAMs, stored data are:
Retained indefinitely without power
Lost when power is turned off
Retained only if periodically refreshed by UV light
Written only once during manufacturing
In a static RAM (SRAM), logic information is stored by:
Charging a capacitor
Setting the state of a bistable flip-flop
Trapping charge in a floating gate
Changing magnetic polarization of a film
In a dynamic RAM (DRAM), information is stored primarily as:
The state of a cross-coupled latch
The resistance of a polysilicon load
Charge on a capacitor
Magnetization of a thin film
Nonvolatile memories are distinguished from volatile memories because they:
Require periodic refresh of stored charge
Retain data even when power is turned off
Use only bipolar technology
Can never be reprogrammed
SRAM speed is usually enhanced by:
Increasing gate oxide thickness
Increasing gate channel length
Scaling down MOS process to shorter effective channel length
Using thicker metal interconnects only
The effective gate channel length Leff primarily affects SRAM:
Standby current
Access time
Packaging type
Radiation hardness
A 256 kb SRAM has approximately the same number of transistors as:
64 kb DRAM
256 kb DRAM
1 Mb DRAM
4 Mb DRAM
As SRAM feature size scales from 5 µm to 0.6–0.4 µm, the primary benefit is:
Decreased density and increased cost
Increased chip area and higher power
Reduced chip area and higher density
Removal of address decoders
The basic SRAM cell is implemented using:
A capacitor and an access transistor
A cross-coupled inverter pair
A single transistor with resistive load
A magnetic thin film stack
In the general MOS SRAM cell schematic, the load elements (L) serve to:
Increase write speed
Provide refresh capability
Offset charge leakage at drains of storage/select transistors
Implement address decoding
When PMOS devices are used as loads in the SRAM cell, the resulting cell:
Is an NMOS R-load cell
Behaves as a CMOS cell with essentially no static current except during switching
Requires external resistors for load
Cannot be used in VLSI arrays
Depletion-load and resistive-load SRAM cells have:
Zero standby current
Lower standby power than CMOS cells
A low level of current flowing continuously, leading to higher standby power
No need for load devices
A full CMOS six-transistor SRAM cell uses:
Four NMOS and two PMOS transistors
Six NMOS transistors
Two cross-coupled CMOS inverters plus two NMOS access transistors
Two PMOS loads and four bipolar transistors
Substituting polysilicon resistors for PMOS load transistors in a CMOS cell:
Increases cell size
Decreases cell size by up to about 30% in double-poly technology
Eliminates the need for access transistors
Makes the cell nonvolatile
Mixed-MOS SRAMs typically consist of:
NMOS cell matrix with high-ohmic load resistors and CMOS peripheral circuits
PMOS cell matrix and NMOS periphery
Bipolar cell matrix and CMOS periphery
DRAM cells plus SRAM periphery
The dual-port static cell shown in the text contains:
Four transistors
Six transistors
Eight transistors with double-ended access
Nine transistors with match circuitry
A content-addressable memory (CAM) cell, as described, uses:
Four transistors and one resistor
Six transistors with one access port
Eight transistors and one capacitor
Nine transistors including match circuitry
A CAM cell is especially used in applications where:
Only the data value is needed
Only the address is needed
Both the contents and the location of the cell must be determined
Only sequential access is allowed
In the six-transistor CMOS SRAM cell, the cross-coupled pair that forms the storage element consists of:
Two NMOS access transistors
Two PMOS access transistors
Two CMOS inverters connected in a loop
Two capacitors and two resistors
In the 6T SRAM cell, the access (select) transistors T5 and T6 are:
PMOS devices controlled by bit lines
NMOS devices controlled by the word line
Bipolar devices controlled by the sense amplifier
Floating-gate devices controlled by VDD
The two internal storage nodes in the schematic of the CMOS SRAM cell are:
The bit and bit lines
The word and sense lines
C5 and C6
VDD and VSS
In logic state "1" for the described 6T cell, which of the following is true?:
C5 is high, C6 is low
C5 is low, C6 is high
Both C5 and C6 are high
Both C5 and C6 are low
For logic state "1" in the 6T cell, the corresponding transistor conduction is:
T1 on, T2 off
T1 off, T2 on, T3 on, T4 off
T1 on, T2 on, T3 off, T4 off
All four transistors off
Compared with full CMOS SRAMs, mixed-MOS and full NMOS designs typically have:
Lower standby currents
Higher standby currents
No standby currents
Identical standby currents
A major advantage of mixed-MOS SRAM technique is:
Nonvolatility
Better scaling and relatively lower power than full NMOS
Elimination of resistive loads
No need for CMOS periphery
The introduction of a chip enable (CE)-controlled power-down mode in SRAMs mainly aimed at:
Increasing write speed
Increasing standby current
Reducing standby power by lowering supply internally
Improving radiation tolerance
In a typical SRAM, horizontal interconnects to cells in the same row are called:
Bit lines
Match lines
Word lines
Sense lines
Vertical interconnects along which data flow into and out of SRAM cells are called:
Word lines
Bit lines
Control lines
Clock lines
In a square 16K×1 SRAM organization with 16,384 cells, a 128×128 array organization requires:
4 address lines total
8 address lines total
14 address lines split as 7 for row and 7 for column
16 address lines split evenly
The primary reason to use a near-square memory array (e.g., 128×128) instead of a single 16K-bit row is:
To simplify timing diagrams
To minimize overall chip area and decoder complexity
To avoid using sense amplifiers
To eliminate word lines
The six-transistor CMOS SRAM cell uses which devices as access transistors?:
PMOS devices connected to bit lines
NMOS devices controlled by word line
Bipolar devices tied to VDD
Floating-gate devices
In the 6T CMOS cell, data are stored as:
Charge on a capacitor
Magnetic polarization
Voltage levels on internal nodes of cross-coupled inverters
Current levels through resistors
The basic CMOS SRAM cell has how many stable states?:
One
Two, corresponding to logic "1" and "0"
Three
Continuously variable
During a READ operation in the CMOS SRAM cell, the bit and bitbar lines are initially:
Both low
Both high (precharged)
Left floating
Driven by the sense amplifier
During a READ of a stored "1" in the 6T cell, the selected word line going high causes:
Both bit lines to discharge equally
One bit line to be pulled slightly lower than the other, creating a differential signal
The cell contents to be destroyed
The word line to power down
The CMOS SRAM READ operation is described as:
Destructive
Nondestructive, the cell state remains unchanged
Requiring a refresh of the cell
Changing the stored data to logic "0"
Writing a logic “1” into the cell is accomplished by:
Pulling both bit and bitbar low
Setting bit high and bitbar low while asserting the word line
Setting bit low and bitbar high
Toggling the supply voltage
Synchronous SRAMs differ from asynchronous SRAMs mainly in that they:
Operate only at DC
Require system clocks and are faster because inputs are clocked
Do not support write operations
Cannot be used with microprocessors
The SRAM periphery that handles READ/WRITE operations is located:
Inside each cell
Only off-chip
Around the cell array, including address decoding and sense circuits
Only in the power supply pins
Typical WRITE circuitry in the SRAM periphery consists of:
Only capacitors on bit lines
Inverters on input buffers and a pass transistor with a write control signal to bit lines
DRAM-style refresh counters
Magnetic drivers
Typical READ circuitry in SRAMs uses:
Single-ended differential sense amplifiers to detect small bit-line differences
Only static inverters directly on bit lines
External operational amplifiers
No amplification, direct connection to pins
The internal data path design in SRAM is important primarily because:
It determines only the packaging density
It largely determines the power-delay product, due to load impedance
It eliminates the need for sense amplifiers
It controls the refresh frequency
Address Transition Detection (ATD) circuitry in a “static” SRAM is used to:
Detect power-down conditions
Detect transitions on address lines to generate internal clock signals
Measure leakage currents in bit lines
Control nonvolatile programming
The earliest semiconductor memories were built using:
CMOS technology
NMOS technology
Bipolar technology
GaAs technology
Modern use of bipolar RAMs is primarily in:
High-density, low-speed applications
High-speed applications
Nonvolatile storage
Ultra-low-power embedded systems
Bipolar RAMs are often:
Bit-oriented only
Word-oriented, requiring two-step decoding
Capacitor-based
Magnetoresistive
A key distinguishing feature of DRAM cells compared to SRAM cells is that DRAM cells:
Are built from 6 transistors per cell
Use capacitors requiring periodic refresh
Store data in cross-coupled inverters
Are inherently nonvolatile
Standard SRAM interfaces are designed to be compatible with:
Only CMOS circuits
CMOS, TTL, and ECL circuits
Only ECL circuits
Only GaAs circuits
For a WRITE operation into the 6T SRAM cell:
Only the word line is toggled
Bit and bit̄ lines are driven with new data before word line activation
Cell must be precharged after write
A refresh cycle is required immediately after write
