Mechatronics - Flip Flops - Chapter 7

Front

Flip-flops are wired together to form sequential logic circuits.

Back

True

Front

Flips-flops are wired together to form combinational logic circuits.

Back

False

Front

The complementary output (Q') of a flip-flop is always at the opposite logic state from the normal (Q) output.

Back

True

Front

To set a flip-flop means to force the normal (Q) output to a 1 or HIGH.

Back

True

Front

To reset a flip-flop means to force the normal (Q) output to a 1 or HIGH.

Back

False

Front

The basic building block of sequential logic circuits is the ______.

Back

Flip-flop

Front

During time period t₁, the R-S flip-flop is in the ____ mode of operation.

Back

Set

Front

During time period t₃, the R-S flip-flop is in the ____ mode of operation.

Back

Reset

Front

During time period t₁, the normal output of the R-S flip-flop is ___

Back

Set to 1

Front

During time period t₂, the normal output of the R-S flip-flop is ___

Back

Held at 1 (in hold mode)