Operating System

Operating System

by Ashish Bhatnagar

​Booting

• ​Booting is the process of loading an Operating System into the Computer's memory 

• CPU sends a fixed memory address to to start the loading point on firmware inside the ROM called as BIOS or UEFI

• POST is executed

• Search for non-volatile storage devices for OS files

• Reads the Boot sector or MBR

• Transfers the OS files into the RAM

​Interrupt

• An interrupt is a signal sent from a device attached to the computer or from a software that the computer is running, which causes the operating system to temporarily stop what it is doing and service the interrupt.

• ​Interrupts allow computers to multitask.

• ​Interrupts and memory buffers works with each other to perform computing operations

​Buffer

• Buffers are temporary areas of memory in a computer​ used for storing the data required for a process to complete.

• ​Buffers are used for processor optimization because peripheral devices work at a much slower rate than a processor.

​Hard Drive Buffer

• Hard Disk Buffer is sometimes called as Disk Cache or Cache Buffer.

• It ​acts as a temporary storage site for data being transferred to or from the hard disk.

• Buffer is used ​for storing some data and then transferring this to or from the Hard Disk. This results in increased speed and more efficient transfer between the computer and the Hard Disk.

• ​Whenever a user is writing large files the cache doesn't boost the transfer speed in any way.

​Computer Architecture

• Based upon Von Neuman architecture​

• It was based on the idea of stored ​instructions and data in a memory.

• ​Data and instructions move between the memory and processor.

• ​Data and instructions are moved between different components by the help of connections called as a Bus

• ​There are three buses

  • ​Data Bus for moving data

  • ​Address bus for moving the address of memory location

  • ​Control bus to carry the control signals

​Von-Neuman Architecture

​Address Bus

• ​It carries the address of a memory location. The address is stored in the form of binary numbers to enable the data bus to access the memory contents.

• ​Address buses are made up of a collection of wires connecting the CPU with main memory that is used to identify particular locations (addresses) in main memory.

• ​The width of the address bus (that is, the number of wires) determines how many unique memory locations can be addressed. ex. 32 bits or 64 bits.

• A system with a 32-bit address bus can address 4 gigabytes of memory space. Newer computers using a 64-bit address bus with a supporting operating system can address 16 exbibytes of memory locations, which is virtually unlimited.

​Data Bus

• A data bus is a system within a computer that provides transportation for data.

• A data bus can transfer data to and from the memory of a computer, or into or out of the central processing unit

• ​A data bus can operate as a parallel or serial bus depending on how the data is carried.

• ​A parallel bus is used in more complex connections that must carry more than one bit at a time. Common examples include Peripheral Component Interconnect (PCI) Express.

• ​Common examples of a serial bus include Universal serial bus (USB) and serial advanced technology attachment (SATA) connections.​

​Control Bus

• ​Carries the control signals around the computer to control the functioning of each component.

• ​It is unidirectional bus. It only sends the signals out from CU

• ​Without the control bus the CPU cannot determine whether the system is receiving or sending data.

• ​The control bus contains a control line for write instructions and a control line for read instructions. A signal is sent into the appropriate line for a read or write operation.

​Control Signals

• ​​Read – signals a memory read operation is to take place

• Write – signals a memory write operation is to take place

• Clock – synchronises the signals being passed in and out of the processor

• Reset – clears all registers and buses of data

• Interrupt – tells the processor to save current process, run interrupt process until completed, then resume its activities (can be ignored)

Register

• ​Aprocessor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of faststorage.

• ​Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data.

​User Accessible Registers

• Data Register used to hold the data required by the CPU for processing.

• Address Register used to store the address of a ​memory location. This address is used to access the memory location in the main memory.

• ​Address of the memory to read from or write to is loaded in to Memory Address Register.

• ​Using this address the read or write operation on the memory location is performed.

Fetch Execute Cycle

• ​A continous process used to perform the execution of instruction in a CPU

• Data and instructions are fetched from the memory and stored in registers

• ​Each instructions is decoded before being executed

• ​Some special registers are used to perform the fetch execute cycle

​Fetch Execute Cycle

• ​The Program Counter contains the address of the memory location that has the next instruction which has to be fetched.

• ​This address is then copied from the PC to the MAR via the address bus.

• ​The contents (instruction) at the memory location (address) contained in MAR are then copied into the MDR.

• ​The contents (instruction) in the MDR is then copied and placed into the CIR

• ​The value in the PC is then incremented by 1 so that it now points to the next instruction which has to be fetched.

• ​The instruction is finally decoded and then executed by sending out signals (via control bus) to the various components of the computer

• ​Repeat all the steps

Fetch​

• ​Program counter stores the address of the next instruction to be executed.

• ​PC starts at 0000 that is the first address where first address is located in RAM

Fetch​

• The computer needs somewhere to store the current address in RAM that it is looking for. This is what the memory address register (MAR) is for. The address 0000 is therefore copied into the MAR.

Fetch​

• A signal is now sent down through the address bus to the RAM. The control unit sends out a memory read signal, and the contents of the address 0000 are copied through the data bus to the memory data register (MDR).

• ​As the data fetched during the fetch stage is an instruction, it is copied into the instruction register (IR).

Fetch​

• As the first instruction has been fetched, the system is at the end of the fetch stage of the cycle. The program counter can be incremented by 1, so the system is ready to read the next instruction when the next fetch cycle starts.

Decode

• Now, the instruction needs to be decoded. It is sent via the data bus to the control unit, where it is split into two parts.

• The first part is the operation code or opcode, which in this example CPU is the first four bits. This is the command that the computer will carry out.

• The second part, in this case the second four bits, is the operand. This is an address in RAM where data will be read from or written to, depending on the operation.

• The control unit can translate opcodes into instructions. So here the control unit translates the opcode 0101 into a LOAD FROM RAM instruction.

Execute

• Now, the command will be executed. The operand is copied to the MAR, as it provides the address of the data to be loaded (0100 in this case).The data at address 0100 is then fetched from RAM and passed up the data bus to the MDR. As it is not an instruction but simply data, it is then passed to the accumulator (Acc).

​01010

​LOAD

2nd Cycle​

• The PC now holds 0001, so you fetch, decode, and execute the instruction at that address.

• ​The PC is at 0001, so this is the next instruction to be fetched.

• The instruction opcode and address operand are placed in the IR, and the PC increased by 1 again.

• The instruction is decoded, while the address of the data to be acted upon is placed in the MAR. The instruction turns out to be ADD, which adds two pieces of data together.

• The new data is fetched from the address and eventually ends up in the accumulator, along with the results of the previous cycle.

• To finish off this stage, the two values in the accumulator are passed into the ALU, where they can be added together, as was instructed by the opcode.

• The result is then placed back into the accumulator.

That’s a second cycle complete.

​01010

​LOAD

3rd Cycle​

• The last cycle is for the instruction at 0010. It uses the opcode 0011, which is STORE and the operand 0110, which is the last address in the RAM shown.

• ​So this cycle takes the results of the addition in the accumulator and stores it back into RAM at address 0110, as requested.

​01010

​LOAD