ICS113 Computer Architecture Overview

Computer Architecture Overview

•CPU's control unit coordinates program execution

2

von Neuman Architecture

Tanenbaum and Austin, Structured Computer Organization, 6/E

•CPU's ALU specializes in solving math and logic instructions

3

von Neuman Architecture

Tanenbaum and Austin, Structured Computer Organization, 6/E

•CPU's registers are very fast memory slots (1 value/register)

4

von Neuman Architecture

Tanenbaum and Austin, Structured Computer Organization, 6/E

•Main memory accessed by CPU as needed; normally random

access (hence random access memory, or RAM)

5

von Neuman Architecture

Tanenbaum and Austin, Structured Computer Organization, 6/E

•Chips have general-purpose registers that can contain anything,

and special-purpose registers that contain only 1 type of value

•PC: Program Counter; contains the memory location of the

current instruction

•IR: Instruction Register; contains the current instruction to be

executed

•MAR: Memory Address Register; contains the memory location to

access in RAM

•MDR: Memory Data Register; contains the data retrieved from

the RAM location indicated by the MAR, or the data to be stored
in the RAM location indicated by the MAR

6

Special Registers

•I/O devices accessed by CPU as needed; random or sequential

access

7

von Neuman Architecture

Tanenbaum and Austin, Structured Computer Organization, 6/E

Draw

Match the terms to what they contain.

Multiple Choice

Which of the following solves math and logic instructions?

• Control Unit

• Arithmetic logic unit

• Registers

• RAM

•The daily life of the CPU…

•Fetch: Get an instruction from memory

•Decode: Figure out what circuitry to involve

•Execute: Carry out the instruction

8

The Fetch - Decode - Execute Cycle

•PC → MAR

•Fetch

•MDR → IR

•PC = PC + 1

(unless
indicated
otherwise by
instruction)

9

Fetch

00

01

10

11
00

01

10

11

RAM

Memory
Decoder

Fetch/Store
Controller

MAR

0

1

0

0

MDR

1

0

1

1

Instruction

Register

Program
Counter

Instruction
Decoder

Control

7

14

21

+

-

x

÷

Registers

Selector

Lines

ALU

=

Multiplexor

<

=

>

Architecture in Context

I/O

Controller

Bus

CPU

Disk

Memory

Cache

•Instruction Identifier (OpCode) → Instruction Decoder

10

Decode

00

01

10

11
00

01

10

11

RAM

Memory
Decoder

Fetch/Store
Controller

MAR

0

1

0

0

MDR

1

0

1

1

Instruction

Register

Program
Counter

Instruction
Decoder

Control

7

14

21

+

-

x

÷

Registers

Selector

Lines

ALU

=

Multiplexor

<

=

>

Architecture in Context

I/O

Controller

Bus

CPU

Disk

Memory

Cache

Multiple Choice

What is the basic operation cycle of a CPU?

• Fetch

  Decode

  Execute

• Fetch

  Execute

  Decode

• Execute

  Decode

  Fetch

• Decode

  Fetch

  Execute

•Load a

value from
location X in
RAM into a
general
purpose
register
(e.g., RA)

•X → MAR

•FETCH

•MDR → RA

11

Execute: LOAD(X, RA)

00

01

10

11
00

01

10

11

RAM

Memory
Decoder

Fetch/Store
Controller

MAR

0

1

0

0

MDR

1

0

1

1

Instruction

Register

Program
Counter

Instruction
Decoder

Control

7

14

21

+

-

x

÷

Registers

Selector

Lines

ALU

=

Multiplexor

<

=

>

Architecture in Context

I/O

Controller

Bus

CPU

Disk

Memory

Cache

•Add values

in registers
RA and RB
and store
the result
in RA

•RA→ ALU

•RB→ ALU

•ADD

•ALU → RA

12

Execute: ADD(RA, RB)

00

01

10

11
00

01

10

11

RAM

Memory
Decoder

Fetch/Store
Controller

MAR

0

1

0

0

MDR

1

0

1

1

Instruction

Register

Program
Counter

Instruction
Decoder

Control

7

14

21

+

-

x

÷

Registers

Selector

Lines

ALU

=

Multiplexor

<

=

>

Architecture in Context

I/O

Controller

Bus

CPU

Disk

Memory

Cache

•Copy a

value in a
general
purpose
register
(e.g., RA) to
location X
in RAM

•RA→ MDR

•X → MAR

•STORE

13

Execute: STORE(RA, X)

00

01

10

11
00

01

10

11

RAM

Memory
Decoder

Fetch/Store
Controller

MAR

0

1

0

0

MDR

1

0

1

1

Instruction

Register

Program
Counter

Instruction
Decoder

Control

7

14

21

+

-

x

÷

Registers

Selector

Lines

ALU

=

Multiplexor

<

=

>

Architecture in Context

I/O

Controller

Bus

CPU

Disk

Memory

Cache

•Compare

contents
of RA and
RB and
set the
appropriate
result
indicators
in the ALU

•RA→ ALU

•RB→ ALU

•COMPARE

•Set <,=,> as appropriate

14

Execute: COMPARE(RA,RB)

00

01

10

11
00

01

10

11

RAM

Memory
Decoder

Fetch/Store
Controller

MAR

0

1

0

0

MDR

1

0

1

1

Instruction

Register

Program
Counter

Instruction
Decoder

Control

7

14

21

+

-

x

÷

Registers

Selector

Lines

ALU

=

Multiplexor

<

=

>

Architecture in Context

I/O

Controller

Bus

CPU

Disk

Memory

Cache

•Get the

instruction
stored in
location X
in RAM

•X → PC

15

Execute: JUMP(X)

00

01

10

11
00

01

10

11

RAM

Memory
Decoder

Fetch/Store
Controller

MAR

0

1

0

0

MDR

1

0

1

1

Instruction

Register

Program
Counter

Instruction
Decoder

Control

7

14

21

+

-

x

÷

Registers

Selector

Lines

ALU

=

Multiplexor

<

=

>

Architecture in Context

I/O

Controller

Bus

CPU

Disk

Memory

Cache

•There are usually also conditional jumps, such as JUMPLT,

JUMPEQ, JUMPGT, which jump depending on what flag is set in
the ALU

Open Ended

Describe the following data flow using arrows (->)?

Compare the

value from

location X and R_B.

•M. Meyers, Managing and Troubleshooting PCs, 6th Ed, McGraw-

Hill, ch. 2, ch. 3, ch. 6

16

Reading

•Explain the von Neuman architecture and the fetch/decode/

execute cycle

17

Key Skills