DIGITAL-FlipFlops

The truth table for an S-R flip-flop has how many VALID entries?

• a) 1

• b) 2

• c) 3

• d) 4

In S-R flip-flop, if Q = 0 the output is said to be ___________

• a) Set

• b) Reset

• c) Previous state

• d) Current state

The flip-flops which has not any invalid states are _____________

• a) S-R, J-K, D

• b) S-R, J-K, T

• c) J-K, D, S-R

• d) J-K, D, T

What does the triangle on the clock input of a J-K flip-flop mean?

• a) Level enabled

• b) Edge triggered

• c) Both Level enabled & Edge triggered

• d) Level triggered

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

• a) The clock pulse is LOW

• b) The clock pulse is HIGH

• c) The clock pulse transitions from LOW to HIGH

• d) The clock pulse transitions from HIGH to LOW

What does the circle on the clock input of a J-K flip-flop mean?

• a) Level enabled

• b) Positive edge triggered

• c) negative edge triggered

• d) Level triggered

What would be the characteristic equation of SR latch corresponding to the K-map schematic shown below?

• a. S + RQ_n

• b. S + R'Q_n

• c. S' + RQ_n

• d. S' + R'Q'_n

Which is the prohibited state/ condition in S-R latch and needs to be avoided due to unpredictable nature of output?

• a. S = R = 0

• b. S = 0, R = 1

• c. S = 1, R = 0

• d. S = R = 1

Sequential circuit contains

• a) No memory element

• b) Atleast one memory element

• c) All inputs applied simultaneously

• d) None of the above

T Flip flop is used as

• Transfer data circuit

• Toggle switch

• Time delay switch

• None of the above