
DIGITAL-FlipFlops
Authored by Sajana E V
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University
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20 questions
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1.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
2.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
3.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
4.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
What does the triangle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Edge triggered
c) Both Level enabled & Edge triggered
d) Level triggered
5.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
6.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
7.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
What would be the characteristic equation of SR latch corresponding to the K-map schematic shown below?
a. S + RQn
b. S + R'Qn
c. S' + RQn
d. S' + R'Q'n
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