ARM Cortex M3

ARM Cortex M3

University

10 Qs

quiz-placeholder

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ARM Cortex M3

ARM Cortex M3

Assessment

Quiz

Other

University

Practice Problem

Medium

Created by

Gayathri T

Used 14+ times

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10 questions

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1.

MULTIPLE SELECT QUESTION

2 mins • 1 pt

The first half word in the 32 bit Thumb-2 instruction________

Determines the instruction length and functionality

Determines the instruction length

Determines the instruction functionality

Determines address fetch

2.

MULTIPLE SELECT QUESTION

2 mins • 1 pt

In little-endian format

The byte with the lowest address in a word is the least-significant byte of the word.

The byte with the lowest address in a word is the most significant byte of the word.

The byte with the highest address in a word is the least significant.

The byte at address 0 of the memory system connects to data lines 31-24.

3.

MULTIPLE SELECT QUESTION

2 mins • 1 pt

Why ARM Cortex M is bit core processor?

Internal registers in the register bank are 32-bits

Data paths are 32-bits

Bus Interfaces are 32-bits

All the three

4.

MULTIPLE SELECT QUESTION

2 mins • 1 pt

The Key feature/s of cortex M3 is/are

Greater performance efficiency, Low power consumption, Improved code density,

Greater performance efficiency, Interrupts

Bit banding

All of these

5.

MULTIPLE SELECT QUESTION

2 mins • 1 pt

The address space in ARM is ______

4 GB

8 GB

16 GB

64 GB

6.

MULTIPLE SELECT QUESTION

2 mins • 1 pt

The sleep modes are invoked by

Wait -For-Event (WFE) instructions.

Wait-For-Interrupt (WFI)

Both WFI and WFE

None of these

7.

MULTIPLE SELECT QUESTION

2 mins • 1 pt

When a subroutine is called, the return address is hold in which register?

Stack Pointer

Interrupt register

Program Counter

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