Digital Electronics Lab Exam- part 2

The truth table for an S-R flip-flop has how many VALID entries?

• a) 1

• b) 2

• c) 3

• d) 4

In S-R flip-flop, if Q = 0 the output is said to be ___________

• a) Set

• b) Reset

• c) Previous state

• d) Current state

The flip-flops which has not any invalid states are _____________

• a) S-R, J-K, D

• b) S-R, J-K, T

• c) J-K, D, S-R

• d) J-K, D, T

Sequential circuit contains

• a) No memory element

• b) Atleast one memory element

• c) All inputs applied simultaneously

• d) None of the above

T Flip flop is used as

• Transfer data circuit

• Toggle switch

• Time delay switch

• None of the above

On a master-slave flip-flop, when is the master enabled?

• A.when the gate is LOW

• B.when the gate is HIGH

• C.both of the above

• D.neither of the above

How many natural states will there be in a 4-bit synchronous counter?

• a) 4

• b) 8

• c) 16

• d) 32

Asynchronous counter is otherwise known as ----------

• Parallel counter

• Ripple counter

• synchronous counter

• None of the above

in ----------- counter output of the last flip flop is connected to the first flip flop

• Ripple counter

• Ring counter

• Johnson counter

• Parallel counter

Following flip flop is used to eliminate race around problem

• SR Flip flop

• JK Flip flop

• Master Slave Flip flop

• D Flip flop