ECE212_Sequential

The register has the following timing parameters

• setup time

• hold time

• c2q delay

• d2q delay

Which sequential element is level sensitive?

• A latch

• A flip flop

• A register

Which of the following statements is(are) not correct?

• The larger the setup time the better

• The smaller the setup time the better

• The larger the hold time the better

• The smaller the hold time the better

The larger the propagation delay of the combinational logic

• the lower the frequency of operation

• the higher the frequency of operation

A negative latch followed by a positive latch forms

• a negative edge triggered FF

• a positive edge triggered FF

• a negative latch

• a positive latch