Lenguaje VHDL
Authored by Viridiana FC
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University
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5 questions
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1.
MULTIPLE CHOICE QUESTION
10 sec • 1 pt
Es donde se declaran los puertos
Entity
Behavioral
Architecture
Process
2.
MULTIPLE CHOICE QUESTION
10 sec • 1 pt
Es donde se encuentre el cuerpo del programa
Entity
Behavioral
Architecture
Process
3.
MULTIPLE CHOICE QUESTION
10 sec • 1 pt
Describe el comportamiento de las salidas con respecto a las entradas
Entity
Behavioral
Architecture
Process
4.
MULTIPLE CHOICE QUESTION
10 sec • 1 pt
Es la opción en Xilinx para crear un nuevo programa vhdl
Vhdl
Vhdl module
View RTL schematics
synthesis
5.
MULTIPLE CHOICE QUESTION
10 sec • 1 pt
Te permite ver el schematic y sus propiedades
View RTL schematic
View technology schematic
Behavioral
Check syntax
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