The approximate external delays at input pin and output pin is defined to STA engine to calculate path delay is at

• Post layout phase

• Pre layout phase

• Inter Layout phase

• Intra layout phase

The command used to define the constraint to set the capacitance on the output port of the circuit is:

• Set_Drive

• set_load

• Set_max_fanout

• set_transition

Indentify the command used to fix the constant value for a port:

• Set_load

• Set_input _capacitance

• Set_case_analysis

• None of the above

To derate any shortest path during OCV analysis the optionused with the "Set_timing_derate" command is :

• -late

• -rise

• -fall

• -early

In below options, how many values can be used for representing digital signal?

• 1

• 4

• infinite

• 2

Which check is perfomed to verify the design whether it follows the lambda based rule

• LVS

• DRC

• ERC

• Back annotation

A sequential element where a multiplexer followed by a D-flip-flop

• RS Flip-flop

• D Flip-flop

• Scan Flip-flop

• T Flip-flop

Why STA is required for design? which is correct option

• Routing

• None of these

• Parasitics

• Speed/ Frequency check

Which is correct option for fall time?

• Signal value from 10% to 90%

• Signal value from 90% to 10%

• Signal value is constant

• None of the above

T-Model and PI model are used for ______

• Cell delay calculation

• Fanin and Fanout

• Interconnect RC calculation

• None of the above