4.7 Review Warm-Up

True or False: In a synchronous counter, all flip-flops are directly connected to the clock signal.

• True

• False

True or False: Synchronous counters experience a more extreme ripple effect/propagation delay than asynchronous counters.

• True

• False

Which is true about the third flip-flop (MSB) in a synchronous up-counter with negative-edge triggered flip-flops?

• The third flip-flop will toggle at every falling edge of the clock signal.

• The third flip-flop will toggle at the falling edge of a clock signal when the flip-flop before it has an output of 1.

• The third flip-flop will toggle at the falling edge of a clock signal when both of the preceding flip-flops have an output of 1.

• The third flip-flop will toggle at the rising edge of a clock signal when both of the preceding flip-flops have an output of 1.

How would you make a synchronous down counter?

• Wire ~Q into J and K and into the AND gate inputs so the flip-flop will toggle when the preceding outputs are 0

• Wire Q into J and K and into the AND gate inputs so the flip-flop will toggle when the preceding outputs are 1

• Change the AND gate to a NAND gate

• Change from a negative-edge triggered flip-flops to positive-edge triggered flip-flops.

True or False: Synchronous modulus counters are made in the same way as asynchronous modulus counters, wiring the inputs and outputs of a NAND gate.

• True

• False