pahc 5.2

What types of memory access are there?

• [<$>] There are 4 types of memory access: sequential access, direct access, random access, memory block access.

• [<$>] There are 4 types of memory access: sequential access, direct access, random access, associative access

• [<$>] There are 4 types of memory access: sequential access, direct access, memory block access, associative access

• [<$>] There are 4 types of memory access: direct access, memory access, random access, associative access

Regarding the method of writing data to Cache, which of the following statements is correct?

• [<$>] Write-through has fast writing speed because you do not have to check whether the corresponding Block in the Cache has been replaced or not.

• [<$>] Write-back writing speed is slow because you have to find out whether the corresponding Block in the Cache has been replaced or not

• [<$>] Write-back has fast writing speed because it only writes to the Cache. When the corresponding Block in the Cache is replaced, the entire Block is written back to main memory.

• [<$>] Write -through (Write-through) slow writing speed because you have to check whether the corresponding Block in Cache has been replaced or not

Given a computer with main memory capacity of 4GB, cache memory capacity of 512KB, line size of 32bytes, memory compartment length of 4bytes. In the case of the full associative mapping technique, the Tag + Word address emitted by the processor to access the Cache is:

• [<$>] 27+3

• [<$>] 29+3

• [<$>] 27+5

• [<$>] 29+5

For random access memory, which of the following is true?

• [<$>] Data in memory has random values

• [<$>] Memory data is read or written at random times

• [<$>] The access time to any memory location in memory is equal

• [<$>] Data in memory is not read or written sequentially

For Cache memory, considering the direct mapping technique, the order of finding Blocks in the cache is done based on the fields in the address emitted by the CPU as follows:

• [<$>] Line -> Word -> Tag

• [<$>] Line -> Tag -> Word

• [<$>] Tag -> Line -> Word

• [<$>] Tag -> Word -> Line

Given a computer with main memory capacity of 512MB, cache memory capacity of 128KB, line size of 16bytes, memory compartment length of 4bytes. In the case of the full associative mapping technique, the Tag + Word address emitted by the processor to access the Cache is:

• [<$>] 22+6

• [<$>] 24+4

• [<$>] 22+4

• [<$>] 24+2

Regarding computer main memory, which of the following statements is false?

• [<$>] Contains programs and data in the form of libraries

• [<$>] Logical management of main memory depends on the operating system

• [<$>] In principle, the programmer can intervene in the entire main memory

• [<$>] Addressed directly by the processor

Given a computer with main memory capacity of 128MB, Cache memory capacity of 64KB, Line size of 8bytes, memory compartment length of 1byte. In the case of the direct mapping technique of the Tag + Line + Word address format emitted by the processor to access the Cache is:

• [<$>] 10+14+3

• [<$>] 11+13+3

• [<$>] 11+14+2

• [<$>] 11+12+4

Characteristics of SRAM memory

• [<$>] No need to refresh periodically

• [<$>] Access time is larger than DRAM

• [<$>] Must be refreshed periodically

• [<$>] The cost per memory bit is lower than DRAM

Given a SRAM memory chip with a memory capacity of 64K x 8bit, which of the following statements is wrong?

• [<$>] The capacity of the memory chip is 64KB

• [<$>] There are 8 data lines

• [<$>] There are 14 address lines

• [<$>] There are 24 address lines and 8 data lines